Converting C-style include file to Verilog?

I have a system that includes both C (for a microprocessor) and Verilog code. Where these components interact, I would like to have a single source file from which certain relevant constants are derived. Initially, at least, I'm looking for a way to simply generate a Verilog file from a 'C' include file. This would be pretty straightforward except for the macros in C. (I wrote one but it's kinda limited, doesn't handle all the C -style math).

Has someone developed a C preprocessor that will do this? I can't seem to get 'cpp' to emit processed values (e.g. purely numerical if multiple levels of macros have been used). Normal development environment is Linux...

Thanks for any ideas/insights!


Reply to
Frank Miles
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Hello Frank.

Some years ago I had a similar problem. I ended up using Python scripts which generated Verilog and C header files on the fly from the same template files written in Python.

The nice thing of using a script language is that you can build and evaluate expressions easily on the fly and that is exactly what I wanted (some other compiled languages allow you to do the same thing, for example using reflection in Java, but you end up writing more code). E.g.

e = "3*4+%(foo)s" d = {'foo': 5} n = eval(e % d) your_function(n) ...

The template scripts were horrible --mixture of numbers, strings, regexp strings, recursive evaluation of regexps...-- but it did the job automatically and flawlessly, and therefore was worth the upfront effort.

Also, Python's re package was very useful because it allows grouped matches and you can perform simple parsing with them.

Luck with your project.

-- PabloBleyerKocik /"I believed that people would become programmers pbleyer / and not need companies as much. You can see how / laughable that was." -- Steve Wozniak

Reply to
Pablo Bleyer Kocik

Just use m4 to generate your C and Verilog header files. m4 is a much more flexible macro processor than cpp.


Reply to
Kelly Hall

Ive got a perl script which does this,but it produces vhdl rather than verilog.Thinking about it making the changes to make it produce verilog might be just as long winded as writting a new perl script from scratch but if you want to see it you are welcome.

Reply to

Thanks for the offer (and I may be wrong), but it sound like such a port would probably really difficult ... especially with my limited perl skills. My current converter, as limited as it is, starts with the C include file. This is in some ways easiest since some of the "constants" are in the form of enums. It's written in python. Perhaps I should look at m4...

While I am disappointed that something isn't already available, I guess that's it. Thanks for your responses!


Reply to
Frank Miles

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