I have a system that includes both C (for a microprocessor) and Verilog code. Where these components interact, I would like to have a single source file from which certain relevant constants are derived. Initially, at least, I'm looking for a way to simply generate a Verilog file from a 'C' include file. This would be pretty straightforward except for the macros in C. (I wrote one but it's kinda limited, doesn't handle all the C -style math).
Has someone developed a C preprocessor that will do this? I can't seem to get 'cpp' to emit processed values (e.g. purely numerical if multiple levels of macros have been used). Normal development environment is Linux...
Thanks for any ideas/insights!