Spartan-3 VCCIO ramp up time

Austin,

you are probably the right person to answer this question:

I made a mistake and now I have a board with a XC3S200FT that has a ramp up time for the 2.5V power supply of only about 300us. That is only about half us much as required by the datasheet.

One I/O bank uses 2.5V as VCCIO, the others use 3.3V which has a ramp up time of 600us.

Apparently the board is working normally. Can anyone comment on what kind of mishap I could expect because of this? If there is a bad effect that does not happen on the prototype, how will it be triggered on future boards: Temperature? Chip to chip tolerances?

Or is the safety margin in the datasheet large enough that I can ignore this?

Kolja Sulimma

Reply to
Kolja Sulimma
Loading thread data ...

If the 2.5V, 300 us ramp is on the VCCAUX supply only, then no problem. However, if one of the VCCO_# supplies also connects to the 2.5V supply, then yes, the design violates the current Tcco specification in the Spartan-3 data sheet (Table 3 of the Spartan-3 data sheet, page 3).

formatting link

The Tcco specification for the XC3S200 in the FT256 package is 600 us (0.6 ms). That's a worst-case value. Most devices, but not all under worst-case conditions, should function with a 300 us ramp rate. Your prototype design should be fine, although Xilinx does not guarantee it with a 300 us ramp rate. Can you ignore it for your production design? Not if you want guaranteed success for every board.

So what happens if you violate the specification? In the XC3S200, you could potentially trigger the aggressive ESD protection circuit. You will see additional current draw, but only if the VCCO ramps too fast. If the power supply doesn't have enough capacity, then the FPGA may fail to configure. If the supply does have enough capacity, then the FPGA will configure, but may still draw current. If the VCCO supply ramps slower than the Tcco specification, then you will never see this condition.

The overly aggressive ESD circuit is tamed in the XC3S50 and XC3S1000 FPGAs available today. There is no ramp limit for these devices. If the ramp-rate is a concern in your design, the XC3S1000 is also available in a pin-compatible FT256 package.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

formatting link

--------------------------------- Spartan-3: Make it Your ASIC

Reply to
Steven K. Knapp

Steven,

As your mention, "If the power supply doesn't have enough capacity, then the FPGA may fail to configure.". Does it effect in only the master serial mode or all configuration mode include JTAG mode?

Channing

"Steven K. Knapp" ?ÈëÓ?þ news:civ1kc$ snipped-for-privacy@cliff.xsj.xilinx.com...

worst-case

design

could

power

FPGAs

Reply to
Channing_W

the

mode

The limitation is if ...

  • The VCCO supply ramps faster than the minimum data sheet specification (Tcco)

and

  • The VCCO supply does not have excess current capacity

then the FPGA may fail to configure. If the supply ramps slower than the specified Tcco, then no problem.

If the supply does ramp faster than Tcco, then the problem could potentially occur regardless of the configuration mode.

Just FYI, the Tcco specifications have already been improved to "No Limit" for the XC3S50 and XC3S1000.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

formatting link

--------------------------------- Spartan-3: Make it Your ASIC

[snip]

(0.6

configure.

but

a
Reply to
Steven K. Knapp

the

mode

The limitation is if ...

  • The VCCO supply ramps faster than the minimum data sheet specification (Tcco)

and

  • The VCCO supply does not have excess current capacity

then the FPGA may fail to configure. If the supply ramps slower than the specified Tcco, then no problem.

If the supply does ramp faster than Tcco, then the problem could potentially occur regardless of the configuration mode.

Just FYI, the Tcco specifications have already been improved to "No Limit" for the XC3S50 and XC3S1000.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

formatting link

--------------------------------- Spartan-3: Make it Your ASIC

[snip]

(0.6

configure.

but

a
Reply to
Steven K. Knapp

I'm missing something. How can it not have "excess current capacity" if it's ramping up too fast?

--
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
 Click to see the full signature
Reply to
Hal Murray

I think he meant 'excess' as in 'spare' - sounds a great little problem they stumbled onto, where too fast a ramp triggers what seems close to a 'latch-up reflex' in the ESD regions. From Steve's description, if you have spare capacity, the chip will come up, but "but may still draw [extra?] current."

-jg

Reply to
Jim Granville

One question: is this strictly a power-up issue, or can it be triggered during operation?

In particular, since the ramp spec. is worse for the leaded packages, could a large transient on the VCCO supply cause the same problem?

e.g., if you configure a PQ208 with many parallel DCI terminations, at the end of configuration the VCCO supply will jump instantly from quiescent to full power ( maybe ~3 amps max. for a PQ208, but by that point you'd have heatsinking problems )

Brian

Reply to
Brian Davis

I don't think this is a problem. The ramp speed issue in only of concern at a voltage threshold around 0.8~1.0 volts. As it was explained to me, when the part powers up, there are a lot of transistors which are turned on initially. Once Vcc gets above about 1.0 volts, everything is biased and the transistors that need to be off are off. But the part draws a lot of current in the meantime as the voltage ramps. If the voltage ramps too fast, the PS can max out on current and for some reason, this will disturb the part and it will not initialize correctly to the point that a power down must be done to correct the problem.

So the problem is that you must let the part draw as much current as it needs as the voltage ramps up. The spec is to let you know how much current you will need for a given ramp rate. Keep the ramp rate slower than the worst case spec and the part will be happy with the current spec'd in the data sheet. After the voltage rises above about 1.0 volts this is no longer an issue regardless of how the spec is written (or interpreted).

--
Rick "rickman" Collins

rick.collins@XYarius.com
 Click to see the full signature
Reply to
rickman

Rick,

This issue is (was) new: the ESD protection of the Vcco pins was firing on a high (very fast) dV/dt. Later mask sets got fixed, but some early mask sets are still in production with this restriction.

Just ramp on slower than that indicated in the data sheet, and everything is fine.

The protection is an active clamp (not a SCR), but it still 'latches,' removal of power is required to reset it.

The circuit can not be triggered in normal operation, as it is only used on the Vcco pins, not the IO pins themselves.

This is NOT the power on current issue that was in Virtex, Virtex E, Spartan 2, and Spartan 2E as you describe it. In thoses cases, the current must be supplied to start up the device. It may have acted like an SCR or clamp, but the mechanism was completely different. As well, all of those devices were characterized, and production screens put in place so that we guaranteed start up if there was at least the amount of current specified in the data sheet present for Vccint.

Subsequent to Virtex E, we designed out the current surge issue for the core. (VII, and all later parts do not have an issue with Iccint at startup.)

Aust> Brian Davis wrote:

Reply to
Austin Lesea

Austin Lesea wrote: : Rick,

: This issue is (was) new: the ESD protection of the Vcco pins was firing : on a high (very fast) dV/dt. Later mask sets got fixed, but some early : mask sets are still in production with this restriction.

Any hints for decoding the top marking for that issue?

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
 Click to see the full signature
Reply to
Uwe Bonnes

Interesting to see 600 microseconds referred to as very fast. :)

Thanks everybody for taking the time to explain things.

--
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
 Click to see the full signature
Reply to
Hal Murray

My question was whether the internal VCCO rail collapse/ringing induced by the parallel DCI startup current transient in a leaded package would be sufficient to trigger the problematic ESD circuit.

The VQ/TQ/PQ packages have a slower VCCO ramp rate spec than the BGA packages, and have only one or two VCCO pins per bank.

As a bitstream with parallel DCI finishes loading, the FPGA experiences the mother-of-all-SSO transients when those split terminators all turn on simultaneously.

back-of-envelope calculation:

If Bank 7 of a PQ208 were configured with 9 LVDS_25_DCI input pairs plus a VRP/VRN pair, the DCI startup current spike for that bank at the end of configuration would be ~400 mA.

That current spike would have to flow through only two VCCO pins, with a lead inductance of perhaps 8~12 nH for pin & wire bond in a PQ208, as these appear to be standard leadframe packages(???).

Guessing at a range of possible values for the internal VCCO rail capacitance and the turn-on edge rate of the DCI terminators, this might produce an on-die VCCO rail collapse or ringing of anywhere from a few hundred millivolts to several volts in amplitude.

Brian

Reply to
Brian Davis

No, it can only be triggered during the power-up sequence.

No, not unless the transient drops the VCCO supply down toward ground, in which case the application would violate a variety of specification.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

formatting link

--------------------------------- Spartan-3: Make it Your ASIC

Reply to
Steven K. Knapp

No, it can only be triggered during the power-up sequence.

No, not unless the transient drops the VCCO supply down toward ground, in which case the application would violate a variety of specification.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

formatting link

--------------------------------- Spartan-3: Make it Your ASIC

Reply to
Steven K. Knapp

No, it can only be triggered during the power-up sequence.

No, not unless the transient drops the VCCO supply down toward ground, in which case the application would violate a variety of specification.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

formatting link

--------------------------------- Spartan-3: Make it Your ASIC

Reply to
Steven K. Knapp
[snip]

The problem that you described is a completely different phenomena from much older FPGA families. This phenomena does not exist on any of the modern FPGA architectures like Virtex-II, Virtex-II Pro, Spartan-3, and Virtex-4.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

formatting link

--------------------------------- Spartan-3: Make it Your ASIC

Reply to
Steven K. Knapp
[snip]

The problem that you described is a completely different phenomena from much older FPGA families. This phenomena does not exist on any of the modern FPGA architectures like Virtex-II, Virtex-II Pro, Spartan-3, and Virtex-4.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

formatting link

--------------------------------- Spartan-3: Make it Your ASIC

Reply to
Steven K. Knapp

At present, the XC3S50 and the XC3S1000 do not have a minimum VCCO ramp rate restriction. The remaining family members do. The Spartan-3 data sheet lists the appropriate specifications (Tcco).

When the restriction is removed for the other devices, we will tie the difference to a top-mark field on the package and indicate the difference in the data sheet.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

formatting link

--------------------------------- Spartan-3: Make it Your ASIC

Reply to
Steven K. Knapp

Sorry if my first post wasn't clear: I'm not concerned about a spec-violating external VCCO supply transient, but rather an internal VCCO rail transient, self-inflicted by the FPGA due to end-of-configuration DCI startup current in the leaded packages.

See my other post from earlier today for a better wording of the question.

The SSO guidelines would normally provide some insight into a max limit on the transient current, but the VQ/TQ/PQ SSO specs were changed from a blank column in previous S3 datasheets to not-even-mentioned in the latest datasheet.

Brian

Reply to
Brian Davis

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.