Hi,
I am designing a PLB architecture and need some help. I read the CoreConnect documentation and found the below
Once a slave has asserted the Sl_addrAck signal the PLB arbiter will wait inde=EF=AC=81nitely for the slave to assert the read or write complete signal. It is up to the slave design to ensure that a deadlock does not occur on the bus due to an address acknowledge occurring without the corresponding data acknowledge(s).
Does any buddy know how can i avoid this situation