To estimate the maximum frequency?

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I already have the RTL code available which is designed for ASIC and
targeted to work at 200Mhz. Now if I want to implement the logic into
FPGA, how can get the idea in advance that how fast my logic can work
on the FPGA? What the best way to calculate this number? Is this
something you have to think about first before you do FPGA design?
BTW, I am going to use the Xilinx VirtexII 6000.


Re: To estimate the maximum frequency?

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It really depends on how the design is done.  If it is implemented to
minimize the logic between flip-flops to four input functions and
arithmetic, you can reach the 200 Mhz target.  If on the other hand it
has layers and layers of logic between flip-flops you may only get a few
tens of MHz.  As a first cut, try synthesizing the design with the
Xilinx as a target using synplify or XST and look at the post synthesis
speed estimates.

--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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