hi, i designed decoder in vhdl and i am going to map that on vertex-II xilinx FPGA. Can any body have the idea how to calculate the power consumption in that design. thanking u all.
- posted
19 years ago
hi, i designed decoder in vhdl and i am going to map that on vertex-II xilinx FPGA. Can any body have the idea how to calculate the power consumption in that design. thanking u all.
if you look on the Xilinx web-site they have power calculation tools, you need to know the resources used and the clock frequency, as far as I can remember. Ben
Here is the particular area on Xilinx's web-site :
Xilinx provides 2 types of power estimation tools - pre-implementation (Spreadsheet and Web) and design-based (XPower).
Both pre-implementation tools are directly accessible from the above site and, as Benjamin points out, require resource and frequency i/ps from the users.
XPower comes as part of ISE and requires a design that has been at least mapped. (It also operates on a placed design or on a placed & routed design.)
All three tools support V2.
Regards,
Brendan
Benjam> if you look on the Xilinx web-site they have power calculation tools, you
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