(Stupid/Newbie) Question on UART

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Hello,

    I am wondering if someone could clear this doubt for me, in case of
UART, the clock speed is 1.8432 MHZ, however it is able to transmit
maximum of 115,200 bps, however even if we are able to transmit at 1
bit per cycle we should be able to transmit at 1,843,200 bps. What is
the rationale for making something go slowly, when it can go much
faster.


PS, I really could not find any suitable group for this question,
follow-ups to a more suitable group are welcome.

TIA
--
Imanpreet Singh Arora


Re: (Stupid/Newbie) Question on UART
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The traditional implementation uses a 16x clock on the receiver.

It looks for the transition on the leading edge of the start bit,
then starts counting. After 1.5 baud times, it samples the first bit
in the byte.  That's the middle of the bit cell.

16*115200 is 1843200

You can use slower clocks, say 8x, but they you will (sometimes) be
farther from the center of the bit cell and errors will be more likely.


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Re: (Stupid/Newbie) Question on UART
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The oversampling not only makes it possible to determine the position of the
start bit, but also it combats the noise and errors. The 16 consecutive
sampled values (each being 0 or 1) are used to decide on the actual bit
value. If most of these 16 samples are 1, it's 1. Otherwise, it's 0. A
better (in terms of error immunity) UART is one that works with a current
loop instead of the regular that works with voltage.

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The start bits help to resynchronize. If the data flow isn't continuous but
often have all ones, the receiver and xmitter clocks may not match each
other well, provided all bits in a byte are decoded correctly. Good hardware
implementations may adjust themselves to the clock offset.

Alex



Re: (Stupid/Newbie) Question on UART
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Exactly. Also note that, with serial line (unlike Ethernet, USB etc), the
pauses between bytes can be of arbitrary time. Only the timings between bits in
a byte are established.

Serial line has no notion of the "packet".

--
Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
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Re: (Stupid/Newbie) Question on UART
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but
bits in


Packetization is an artificial thing. Normally, the physical data channels
are continuous and bear no idea of any data packetization. Packets are just
a way to transfer data in portions, which is most useful in the channels,
where the data can be lost or corrupted. Chunks of data are numbered and
redundancy is appended to make sure anything lost or corrupted can be
requested for retransmission. Another way to combat data corruption is to
add the redundancy into the data itself, by some forward error correction
(FEC) mechanism. The receiving party can recover some errorneus bits in the
data from the data with added redundancy. Although FECs can help a lot,
they're not always practical because they require bigger bandwith and of
course not every error can be corrected with them (the Hamming distance of
the FEC determines the correcting performance).

Alex



Re: (Stupid/Newbie) Question on UART
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Oh no.

The Ethernet packet cannot have pauses between bytes, it is transmitted as the
single entity time-wise. Same are USB packets, though they are smaller.

Serial UART has no notion of such mode at all. This is why it is called "async"
in Cisco IOS.

There are also some serial attachment cables which have the notion of the
packet (transmitted as single entity time-wise, I also expect this interface to
have packet headers). They were used in X.25 equipment, and are incompatible
with UART cabling. Cisco IOS called this interface "serial".

The PPP protocol requires the packet-based underlying physical media. So, to
run PPP over the UART line (which means - usual modem) - escape bytes are used
to denote the packet boundaries. It is described in the PPP RFC as appendix. In
Windows, this logic is in AsyncMac.sys which "packetizes" the serial UART line.

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Another very, very major purpose of packetization is time-sharing the single
physical media line for several traffic flows.

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Most network media do not use ECC, they use the stupid checksums. The recovery
is done via retransmission. ECC is used in storage, not networking.

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Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
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Re: (Stupid/Newbie) Question on UART
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to
correction
recovery


If the retransmissions are very costly (e.g. half-duplex physical channels)
but the BER (Bit Error Rate) is good enough, error correction is quite
efficient.

Alex



Re: (Stupid/Newbie) Question on UART
On Sat, 12 Mar 2005 16:36:31 +0300, "Maxim S. Shatskih"

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Actually with 10mb/s Ethernet and USB (all speeds) there is no carrier
on the wire when actual data is not begin transmitted. Clock recovery
starts at an arbitraty point with every packet.


Re: (Stupid/Newbie) Question on UART
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Same as with serial UART.

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USB packets have a preamble to synchronize the PLLs. IIRC Ethernet too.

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Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
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Re: (Stupid/Newbie) Question on UART
On Fri, 09 Jun 2006 04:54:30 GMT, "Maxim S. Shatskih"

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There are no clock-recovery PLLs in USB. FS/LS is specifically
designed to be implemented by a 4x DLL. One can implement 10BT without
a PLL too.

Re: (Stupid/Newbie) Question on UART

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of
transmit
1
is
bit
of the
consecutive
bit
A
current


Pardon me for being a novice. But, are you saying that in actual 16
samples will be transmitted of a single bit. And that the reason, we
have the maximum transmission rate is because 16 copies of a bit will
be transmitted.


--
Imanpreet Singh Arora


Re: (Stupid/Newbie) Question on UART
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No. The 16 samples-per-bit is done on the receiving side. The receiver's
sample clock is not locked to the transmitter's. So, because of this, it
needs to sample many parts of what it thinks may be one bit. To determine if
that bit was truly a one or a zero, many samples are taken. If, for example,
10 of the 16 samples were the same polarity, then it's safe-to-assume that
the bit was that particular polarity.

If the transmitter sent a clock along with the data, then the receiver could
use that clock to sample the data only once (the same as just latching the
data with its clock).

If the transmitter didn't send a clock, but rather sent all data bits in a
very periodic manner, then the receiver could use the data edges to infer
(recover) where the center of each bit is. This method requires a fairly
constant flow of data edges. Because of this, the data is usually scrambled
to insure that this edge density requirement is met.

These two methods of data transmission are referred to as "synchronous"
transmission.

On the other hand, a UART (what you're talking about) is used to send and
receive data "asynchronously". Therefore the receiver doesn't really know
where each data bit is supposed to be (in time). So, sampling and (some sort
of) majority decision making is required. Hence, the lower data rate.

Bob



Re: (Stupid/Newbie) Question on UART
Thanks everyone.

--
Imanpreet Singh Arora


Re: (Stupid/Newbie) Question on UART
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No, I dont think most UARTs work in this way.
The reason for oversampling is to have
a good determination of the sample point.

The UART first tries to determine the middle of the start bit
oversampling by 16, then it only samples once per bit.

If you are sampling at the BAUD rate, then the error in the sample poin
can be almost half a bit in both directions.

If you are sampling at BAUD*16, then the error is 1/16 or 6,25%.

On top of that error you have a deviation between the senders or receivers
frequency vs the nominal BAUD rate.
They can deviate in differing directions.

After receiving 10 bits, your max deviation should be less than half a bit
time.

So the equation is 0,0625 + (10 x 2 x err) is less or equal to 0,5
solving the equation gives err </= 2,19%

If you sample once per bit then your initial error is 0,5

    0,5 + (10 x 2 x err) </= 0,5

This will work only if there is NO deviation between the clock frequencies.
I.E: you need to have a common clock.

If you sample 2 times per bit you error is 0,25
    0,25 + (10 x 2 x err) </= 0,5

    err </= 0,0125

    So your receiver and transmitter must be much more close to each other.

You can apply tricks which resynchrouize the receiver when an edge is
detected
but when you tranmit 0x00 you will have a low start bit followed by
8 low bit so there are no edges.



****************________________****************

start bit is used to determine the sample



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--
Best Regards,
Ulf Samuelsson
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Re: (Stupid/Newbie) Question on UART
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Yes, that's why it uses start and stop bits.

--
Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
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Re: (Stupid/Newbie) Question on UART
Alexei A. Frounze wrote about UARTs:
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I've never seen a UART that behaves that way.  Such a UART would be
very unreliable, because if the sender was slightly slow or fast relative
to the receiver, the 1 bits would get smeared into adjacent bits.

Normal UARTs find the leading edge of the start bit, then wait 8 clocks
and sample again to make sure the start bit is valid.  After that, they
take a single sample every 16 clocks.

Some of the fancier UARTs (e.g., some Motorola/Freescale microcontrollers)
take samples at 7, 8, and 9 clocks into the bit cell, and will report noise
if they are not all equal.

Eric

Re: (Stupid/Newbie) Question on UART
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Another example : The 80C51 UART sampled 3 times, in mid-bit, and does a
majority vote. It does not flag any errors on this.

Some UARTs start looking for a START egde, at the END
of the Stop bit. As an excercise, consider if this is a good idea, and
if not, what would be better ?

jg


Re: (Stupid/Newbie) Question on UART
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Wehn I have done UARTs, I put the filter before the start bit detector
so if there is is a glitch in the beginning of the start bit, then this is
filtered away,
Come to think ábout it,
this might be a bad idea if there is a positive spike after the start bit is
detected,
DO we know for sure that it is only the middle of the startbit that is
filtered
or is the start bit edge filtered as well.
Some UART detect 8 valid samples low and some only
sample half a bit time after the first low is detected.

Any comments on what is good and what is bad?

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Aint a good idea if the sending UART is faster than the receiving UART.
Then you will sample at your perceived end of stop bit
and the sender has at that time already started sending the next startbit
Eventually you will lose one character.
Have to start searching for the startbit after 3/4 or shorter depending on
error.

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Ulf Samuelsson
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Re: (Stupid/Newbie) Question on UART
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On a slightly different note, does anyone know why most serial protocols
use simple voltage levels to denote a logic 0 or 1?  I admit I'm no expert
but I recall from my A-level electronics an edge-triggered system where a
'0' would be (say) low-followed-by-high whereas a '1' would be
high-followed-by-low.  Yes, this means _at_least_ twice as many voltage
transitions per bit but I would have thought that given its greater resilience
mismatched clocks or any stray capacitance it would be worth the trade off.

Just curious...

--
Andrew Smallshaw
snipped-for-privacy@sdf.lonestar.org

Re: (Stupid/Newbie) Question on UART
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  This is used already, and is called Bi-Phase or Manchester encoding,
for the two phase variants of this Clock+Data Scheme.
-jg


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