Hello,
i have the following problem: i try to latch external data (AD7...AD0) into an internal FPGA register on the rising edge of an external signal (address latch enable = ALE). Generally this seems to work, but i often have situations where a very short peak is on the signal ALE. Peak is around 20 ns (can measure them with a scope), whereas my normal signal is around 12 us (600 times longer).
What is a common way of handling this ?
1) I read on some webpages that there is a VHDL mechanism called delay_mechanism (with "reject" or "after" statement). I tried it on target FPGA, but it seems not to work. Could it be that this works only for simulation ?2) I found a lot of articles about doing an RC at the input side. How do i calculate the values of R and C e.g. when i want to ignore all pulses below
50 ns ?3) Is there any method to do it FPGA internal ? Don't want to add external hardware... read of bad ways with delay lines.... i think i read somewhere of reserved words like "SKEW", "SLOW", "FAST". Do they help me ? Should i go in this direction ?
4) Or must i add an external clock only for this ? E.g. with a counter, only when certain count value is reached, the line is valid ?Regards,
Martin