Hi everyone!
I've run into a problem with a design I'm working on and I hope someone may have had a similar problem before. I have a narrow but deep SelectRam with some data in it, that I am trying to read into a std_logic_vector. The problem is when I try to synthesize the design using Synplify Pro, it gives me the following error:
"Expecting constant expression"
which refers to this line of code:
q_out_buff(q_up_idx downto q_idx)