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Interpret a VHDL statement within a serial to paralell port

First, thank you for taking the time to consider the questions I have not a nswered. I am working on a 32 bit serial to 32 bit parallel port which reads from an ADC. Currently looking to find a better solution, and I searched for prede fined vhdl module with little success. I stumbled upon Macros, SR16CE, whic h utilize primitives but they seem to be schematic oriented and not availab le inside the ISE 8.2i, windows xp os.

Question: Do common VHDL constructs exist in some library within the Xilinx folder file structure?

Stumbling onto some help files within Xilinx website,http://www.csit-sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode8.html, I found what I think I was lookin g for, however I need some help interpreting the VHDL statement that does e verything, [line 13]:

8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Parallel Out Note For this example XST will infer SRL16.

1.library ieee;

2.use ieee.std_logic_1164.all; 3.entity shift is
  1. port(C, SI : in std_logic;
  2. PO : out std_logic_vector(7 downto 0));
6.end shift; 7.architecture archi of shift is
  1. signal tmp: std_logic_vector(7 downto 0);
  2. begin
  3. process (C)
  4. begin
  5. if (C'event and C='1') then
  6. tmp
Reply to
nobody
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answered.

an ADC. Currently looking to find a better solution, and I searched for pre defined vhdl module with little success. I stumbled upon Macros, SR16CE, wh ich utilize primitives but they seem to be schematic oriented and not avail able inside the ISE 8.2i, windows xp os.

nx folder file structure?

ing for, however I need some help interpreting the VHDL statement that does everything, [line 13]:

el Out

The "&" symbol in Line 13 is the concatenation operator. Line 13 performs t he shift by concatenating the lower 7 bits of the shift register with the s erial input, SI. This results in SI becoming bit 0 of tmp and bit 7 of tmp being discarded. Hope this helps.

Darol Klawetter

Reply to
darol.klawetter

Yes, that is a fairly straightforward expression of the shift function. The question is whether your tool will be able to infer the use of two SRL16s. Actually, I don't think an SRL16 is at all appropriate for a serial to parallel converter since it doesn't have a parallel output. The SRL16 is serial buffer, 1 bit in and 1 bit out.

If you look at the various sections on this page they list examples some of which say they *will* infer SRL16s and some say they *will not* infer SRL16s. I think they made a mistake and left out the *not* for the section showing this code. This is *not* Xilinx vetted info. It is a third party source with unknown credentials. I believe any of the code shown involving parallel input or output will not be inferred using SRL16s.

Look at this app note and I think you will see the limitation of the SRL16s.

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So the above code will work just fine. It just won't, and in fact,

*can't* use an SRL16.

Someone please correct me if I am wrong.

--

Rick
Reply to
rickman

not answered.

om an ADC. Currently looking to find a better solution, and I searched for predefined vhdl module with little success. I stumbled upon Macros, SR16CE, which utilize primitives but they seem to be schematic oriented and not av ailable inside the ISE 8.2i, windows xp os.

ilinx folder file structure?

ooking for, however I need some help interpreting the VHDL statement that d oes everything, [line 13]:

allel Out

ms the shift by concatenating the lower 7 bits of the shift register with t he serial input, SI. This results in SI becoming bit 0 of tmp and bit 7 of tmp being discarded. Hope this helps.

s.

Thank you for you time. I had similar thoughts having read xapp465. I guess that still leaves me with needing a helpful solution toward utilizing a se rial to parallel hardware, which would seem very common and tucked away in some library somewhere. I came across the use of macros, but are based on g raphical symbols, schematics, and not VHDL. The macors seemed to be based o n the SR16CE but I have not been able to find hide nor hair of such a beast . Thank you!

Reply to
nobody

e not answered.

from an ADC. Currently looking to find a better solution, and I searched fo r predefined vhdl module with little success. I stumbled upon Macros, SR16C E, which utilize primitives but they seem to be schematic oriented and not available inside the ISE 8.2i, windows xp os.

Xilinx folder file structure?

looking for, however I need some help interpreting the VHDL statement that does everything, [line 13]:

arallel Out

orms the shift by concatenating the lower 7 bits of the shift register with the serial input, SI. This results in SI becoming bit 0 of tmp and bit 7 o f tmp being discarded. Hope this helps.

Darol,

Thank you, that was helpful!

Cy

Reply to
nobody

(snip)

(snip)

Yes, but I think you can select which bit it is.

It will at least make constant length shift registers with lengths other than 16.

The logic is similar to the usual LUT logic, but with the ability to shift the bits in the LUT (RAM).

I am not so good at figuring out Xilinx primitives, but I did figure out how to use a clock generator as a Xilinx primitive.

I think you should be able to generate a shift register, counter, and multiplexer, to shift and then select which bit to send out. It might take primitives to do that, though.

-- glen

Reply to
glen herrmannsfeldt

I'm not sure what you are trying to do. The code you have above will do the job of a serial to parallel shift register. Why do you need to worry about which primitives get used in the FPGA?

--

Rick
Reply to
rickman

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