synchronizer and Reset question?

Looks ok, but I didn't try it. I attached a more generalized example below.

I would leave the reset in unless there is a real good reason not to.

Yes, if the power-up reset is not already synchronized.

-- Mike Treseler

-------------------------------------------------------------------------------

-- Synchronizer Example Thu Jun 24 11:45:45 2004 Mike Treseler

-- Handles in_len inputs and outputs

-- vsim test_dqdq -do "add wave *; run -all"

------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity dqdq is generic (in_len : positive := 4; pipe_len : positive := 2); -- 2 or 3 -- normally 2 levels of synchronization [dq][dq] Watch for reg dups -- 3 levels covers synthesis register duplication [dq][dq]-.-[dqa] -- Provides min of two non-duplicated stages \-[dqb] port ( clk : in std_ulogic; rst : in std_ulogic; raw : in std_logic_vector(in_len-1 downto 0); -- unsychronized cooked : out std_logic_vector(in_len-1 downto 0) -- sychronized ); end dqdq;

architecture synth of dqdq is

signal A,B,C,D : std_ulogic;

-- Example of internal synchronized signals for another process

begin synchronize: process (clk, rst) is -- purpose: put two d flops in line with input vector subtype vec is std_logic_vector(raw'range); variable cooked_v : vec; type shft is array (1 to pipe_len) of vec; variable pipe_v: shft; constant clr_pipe : shft := (pipe_v'range => (vec'range => '0')); procedure sync_this ( i_arg : in std_logic_vector; -- unsynch input vector p_arg : inout shft; -- pipeline shifter o_arg : out std_logic_vector) -- synched output vector is begin p_arg := i_arg & p_arg(1 to pipe_len-1); -- shift in i_arg vec o_arg := p_arg(pipe_v'length); -- output vec off the end end procedure sync_this; begin if rst = '1' then pipe_v := clr_pipe; cooked raw, p_arg => pipe_v, o_arg => cooked_v); cooked