:> >I concur. The SRL16 structure is different from a conventional :> >flip-flop. Although it is only the Master latch in a flip-flop that is :> >reponsible for metastability (the Slave just does the read-out), this :> >might imply that there is no difference. But I still would be leary to :> >venture into untested territory. :>
:>
:> >> Hi Hans-Juergen, :> >> Try a search on Google groups "metastability srl". Top answer is a :> >> discussion we had here called "Should I worry about metastability". :Xilinx's :> >> expert, Peter Alfke, said :- :> >>
:> >> I will not guarantee that SRL16s recover as fast from metastability as :> >> the "normal" flip-flops that I documented, since SRLs are implemented :in :> >> a different circuit design. (Different might mean better or worse). :>
:> Mike Tresseler wrote :> >> Is there any difference w.r.t metastability in using SRLs :> >> compared to FDs? :>
:> >Don't know. Check the data sheet. :>
:> >Or check fmax, with and without a reset. :>
:> Hey, thank you all for answering! :>
:> The fmax of a single SRL seems to be way beyond the :> capacity of the global clock nets. (At least for Spartan2E, that is) :>
:> If I do something like - :>
:> p : process(clk) is :> signal s1, s2 : std_logic; :> begin :> if clk'event and clk='1' then :> s1 s2 Q end if :> end process; :>
:> - I'll get an Fmax of 561Mhz on a XC2S50e-7 !!! :> At least WP4.2's timing analyzer seems to think so... :>
:> But anyway, I guess I'll stick to throwing FDE's at all that :> nasty stuff coming from the outside... :>
:> Regards Hans :>
:> P.S: :>
:> If you think, you found an easy way of doing something in VHDL, :> you're probably doing it wrong. :o) :>
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