edge reset

This is asynchronous design which should be avoided.

No synthesizer will accept it, because there is no way to synthesize it. Think hardware ;) The clk'event and clk='1' is a indication to the synthesizer that you want a flipflop on the outputs after the combinatorial logic you describe in the process. There can only be one such statement.

This is the way:

signal reset_0,reset_1; signal cnt:integer; process(clk) begin if a_rst='1' then --asynchronous reset in cnt

"Jeroen" skrev i en meddelelse news:41513083$0$78738$ snipped-for-privacy@news.xsall.nl...

Thanks for the answer. I have created the following from your description

p_pps_edge : process(rst, clk) begin if (rst = '1') then pps_edge_old

"Rune Christensen" skrev i en meddelelse news:415148e7$0$232$ snipped-for-privacy@dread12.news.tele.dk...

When I used Modelsim Xilinx Special Edition the first attempt didn't work and I have changed it to

p_pps_edge : process(rst, clk) begin if (rst = '1') then pps_edge_new

well that's the way i always do it you could also make the pps_edge registred with a FF

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