Virtex 4 integrated A/Ds?

Michael,

Yes.

The 200Ks/s successive approximation converter eight differential 1 V p-p inputs, as well as the Vccint sense channel, and the temperature sense channel. There are alarm registers for all channels, and various modes it can operate in. Upon power up, before configuration, the A/D is in monitor mode, and outputting data if needed using a JTAG command.

The temperature sensor has a shut down feature to prevent operation in excess of the absolute maximum specified ratings.

The primary purpose for the A/D is to sense internal voltages, and the die temperature. I don't know how many times you have wanted to know the die temperature, but we need to know that quite often, especially when someone claims that the device is not meeting timing (which it usually is, except they are running it at 110C!).

Lots to learn here about what the A/D might be useful for. One application is to detect tampering in security applications, among others.

Aust> Does anyone know if it is possible to use the "system monitor" analog

While the subject is open, Austin why doesn't Xilinx integrate higher performance A/Ds on board. Say 60 Msps, 10 to 12 bits would be nice. Is it a matter of market demand?

Jerry,

Well, that is a good question. Since we are the first to ever put an A/D on an FPGA, I would suggest that it is not as easy as you suggest.

PLLs, Serdes, A/D, all have a similar problem: they want it quiet!

Problem with a FPGA is that generally speaking, they are not very quiet at all.

It is a significant challenge to put a very sensitive circuit right next to a 50KW transmitter, and expect it to not be affected by it.

Also, making analog elements in a straight CMOS logic process is no simple task either. Digital process guarantees that the transistors switch on, and off, quickly. That is about it. Try to make an analog design in a digital process that will yield 100%.

All extremely challenging, and by no means a solved problem.

Once we have a proven A/D technology that meets all requirements, then we can discuss market needs. Until then, the system monitor is a relaxed application (temperature, voltage) that does not require the kinds of static and dynamic specifications that challenge most A/Ds.

The DLL grew into the DCM/PMCD...etc. Other fetaures have also grown and improved with time in subsequent generations. The A/D is just one more element in that 'toybox.'

Aust> While the subject is open, Austin why doesn't Xilinx integrate higher

What is a Serdes?

How will you know the requirements if you don't discuss market needs. For example, we use FPGA in mechatronics, that means sample frequencies of about 100kHz are sufficient. Therefore we use a Delta-Sigma-ADC, which generates other requirements as a Flash ADC for example.

Bye Tom

Serializer/Deserializer; any of the various serial physical layer transceivers which invariably include a clock recovery circuit ie pci express, rocket io etc etc.

Thomas Reinemann wrote: : Hi Austin,

: Austin Lesea wrote: : > PLLs, Serdes, A/D, all have a similar problem: they want it quiet! : What is a Serdes?

: > Once we have a proven A/D technology that meets all requirements, then : > we can discuss market needs. : How will you know the requirements if you don't discuss market needs. : For example, we use FPGA in mechatronics, that means sample frequencies : of about 100kHz are sufficient. Therefore we use a Delta-Sigma-ADC, : which generates other requirements as a Flash ADC for example.

But most peripherals can be bought with some serial interface. You only need about 4 FPGA pins to communicate with these devices. So having an ADC onchip the FPGA is not worth the effort, beside for monitoring the FPGA status itself.

And the requirements for the ADC differ in such a big way for different users.

Bye

Perhaps Broadcom and Silicon Labs should start making FPGAs. :)

Jake