Trace length matching in VHF digital circuit with close chips - needed?

Hi all.

I'm having some difficulty, and the Internet is really, really stingy with the answers. I need expert opinion.

I want to interface a FPGA to a DDR2 chip at 166 MHz. If I put the two chips side-by-side, do I *need* to length match the traces?

I've calculated that the biggest difference in trace lengths in my design is less than 1.8 cm (less than about 0.7 inches). If I put the two chips next to each other - say 1 cm clearance - the longest connection is going to be maybe 3 cm. Now, that's a lot of difference, relatively speaking, but 166 MHz is reeeally, really slow. The difference in arrival/departure time caused by the absolute length difference works out to about 60 ps. This is really supposed to be only about 2-3% of pulse length for data lines. Will this *actually* matter to the chips?

For reference, I'll length match the differential clock. Fortunately, all the pins align just right.

A lot of this uncertainty was sowed into my head by AN2582 from Freescale Semiconductor.

Reply to
Aleksandar Kuktin
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I would hope that there's a specification on how much the trace length can vary -- is such a thing there, or not?

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Reply to
Tim Wescott

ktin:

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eries-DDR2/td-p/551665

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Reply to
lasselangwadtchristensen

My experience is that the lengths are not terribly important unless you are using 166MHz DDR2 memory and clocking this at its maximum specified clock rate. If you use 200MHz memory for instance that gives you an extra 500ns of margin.

I tuned DLLs in the FPGA for the DDR2 clock and strobes for maximum reliability, which was to find where errors crept in at each extreme of delay and choose the centre.

YMMV

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Mike Perkins 
Video Solutions Ltd 
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Reply to
Mike Perkins

The DDR spec is usually just setup and hold times, and of course clock speed.

This should give you all the information you need.

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Mike Perkins 
Video Solutions Ltd 
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Reply to
Mike Perkins

Hi Aleksandar,

you certainly do not need to length match the traces. I have done it for 133 MHz clocked DDR1 and have had no issues for many years now.

Take a look at the board (it is a recent version but the processor/DDR have been unchanged):

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As you see, no length matching. The termination resistors are overkill I live with; I have seen memory work with one or two of the parallel ones missing but I am not sure I can scrap them all so I just have never tried (I am almost certain it will work OK with no resistors, serial ones just shorted parallel ones missing but I have done this only on SDRAM at 100 MHz some 16 years ago).

At these speeds matching to 0.1mm as they typically suggest is simply nonsense. Of course you will route things the right way - i.e. keep things straight and short, make sure they cross no discontinueties on the plane underneath etc. and everything will be all right.

Dimiter

------------------------------------------------------ Dimiter Popoff, TGI

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Reply to
Dimiter_Popoff

You have been very lucky, perhaps in part because SDRAM doesn't have any strobes or other clocks.

While you may get away without terminations for data lines, I cannot recommend leaving out terminations for clock and strobe lines. DDR memory should have its own internal termination resistors according to the type of memory.

As someone who troubleshoots DDR designs, termination resistors are needed on clock and strobe lines. Thankfully most FPGAs have these resistors in both series and parallel forms.

I entirely agree on this point, as long as we are not working at the maximum specified clock frequency.

I have generally tried to ensure all the traces are on one layer, usually possible with FPGAs.

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Mike Perkins 
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Reply to
Mike Perkins

I recently had a design with very occasional errors writing to NAND flash. After a ridiculous amount of time trying to sort out the flash we realized that the 500MHz DDR3s were being used at 800MHz. They had passed every memo ry test, which we thought were aggressive. Running the DDRs at 500MHz or fi tting 800MHz both cured the NAND failure. Moral to the story, if you don't length match you will never know that you didn't need to. Also remember to find out the trace lengths on the IC packaging.

Colin

Reply to
colin_toogood

In part I agree, but this sounds more a flaw in the design that hasn't taken into account the skew in track lengths. Most PCB CAD packages can tell you the max and min lengths of a bus.

It takes an inordinate amount of time to match track lengths and sometimes a compromise is required in return for a faster part or a lower clock speed.

My experience is similar to yours, where on the edge, you get the occasional bit errors, fine in some applications but disastrous in others.

Some processors calibrate the clock - data timing, in others its a manual set once and hope for the best over time and temperature and different batches.

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Mike Perkins 
Video Solutions Ltd 
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Reply to
Mike Perkins

Lucky me, yeah. LOL, I must have been born with a huge supply of luck, has never run out last 30+ years for a single design. Reading the datasheets and thinking can't have had much impact?... :-)

Here is the "lucky" board, built 16 years ago:

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(first revision, the one still at my desk, shot taken after perhaps 10 years of service - perhaps I have had to glue the fan to the CPU again, not sure).

Here are some more details on how I have been lucky to route it: (SDRAMs on both sides, 9 of them, 8 only soldered):

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100 MHz SDRAMs used to work fine as 100 MHz.

DDR1 has no internal terminations, IIRC DDR2 does not have either (not so sure about the latter).

Actually this is valid at the maximum clock frequency for my DDR1 design all day. Have used various types, speeds manufacturers. Never any issue at all, there is quite some margin with these (at 133 MHz clock).

With faster DDR one has to do each byte with its strobes on one layer, yes. Would be insane not to at GHz range clock frequencies. In fact I have kept these in one layer on the DDR design I posted a photo of, too. But no length matching - a few ps are just negligible at 133 MHz clock, there is enough margin not to woryy about it at all.

Dimiter

------------------------------------------------------ Dimiter Popoff, TGI

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Reply to
Dimiter_Popoff

Nope he said they in mistake OVER clocked 500 MHz parts at 800MHz, going beyond spec of chips NOT trace length on PCB. Correctly clocking devices WITHIN spec resolved the problem.

Not what he said read above. For majoprity of designs with a FEW chips (like 1 to 4), as long as you know what the propagation delay is between min and max length and this will be within tolerances you are fine. Concentrate on keeping clocks and strobes si8milar lengths and if possible data shorter. Higher the speed yes ensure terminations are there.

Avoid major dispaities.

When you consider DIMM modules I am sure most tracks are kept short, keeping them ALL smae length will be nigh on impossible. If you are dealing with DIMM modules the length disparity I am sure is more than

0.1mm from driving chip die to each die on each DIMM module. You could get that difference between different data lines with both die.

Seen too many cases of getting exact track length match made the bus go all round the houses and cross many other signals. In most of these cases it was one or two RAM devices. Max track length 50mm in some cases.

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Paul Carpenter          | paul@pcserviceselectronics.co.uk 
    PC Services 
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Reply to
Paul

DDR2 has internal (on-die) termination. Can be turned on or off.

Right, understood.

Reply to
Aleksandar Kuktin

Not that I am aware of, no. :( The closest I could find is the quoted application node from Freescale.

These are present, however. These clock speeds are a new area for me. I'm as conservative as I can be, so I asked before committing. Hardware is no software. :)

Reply to
Aleksandar Kuktin

Thank you.

Reply to
Aleksandar Kuktin

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