I'm trying to do a modular design, building a core, placing it, creating an RPM then going on to a sibling or (finally) parent core, doing the same, etc.
I've noticed something very odd - it seems the P&R can place, route and statically-time a layout which the mapper can subsequently reject with 'Slice XXYY cannot do X,Y,Z at the same time' errors if it is fed the layout as a floorplan.
My main objective has been to see if it's best to lay out on a32-clb-high array (with 32-bit carry chains only taking 16 CLB's, for example), or to do everything on a 16-CLB-high array and having much more depth to the datapath.
I got to the stage in the 16-CLB high layout where the maximum frequency dropped from 50 MHz down to 40 for a very thin wrapper around it. I wanted to test the same level of abstraction with a 32-CLB-high layout.
So, I was creating the RPM layout, and running translate/map/par (T/M/P) periodically to check things were still ok, and it got to the point where the automatic layout was pretty much getting there - there were still a few elements placed "outside" the rectangle when they could have been inside, but I was reasonably happy, given that I just wanted to see if it took the same hit as the 16-high CLB layout.
So, I did a 'copy from placement' into the editable area, and moved the3 or 4 elements from their placed places to ones within my rectangle for the design. I then tried to T/M/P it, and got errors from areas of the design I hadn't touched.
I thought I must have clicked on something, so I did a 'copy from placement' and 'save' immediately, then ran another T/M/P. I still got errors - it seems that the output of the P&R doesn't work as input into another round of T/M/P ...
I also noticed that the RPM where the problem was had been split down the middle (surely the point of an RPM was that this didn't happen), and I suspect the mapper is complaining that the RPM it's picking up from the 'rpm_core' directory (in this case an add/sub module) doesn't match the addsub module geometry that was placed in the design on the last pass:
ERROR:Pack:679 - Unable to obey design constraints (LOC=SLICE_X18Y20) which require the combination of the following symbols into a single SLICE component: MUXCY symbol "as/Madd__n0002_inst_cy_0" (Output Signal = as/Madd__n0002_inst_cy_0) MUXCY symbol "as/Madd__n0002_inst_cy_1" (Output Signal = as/Madd__n0002_inst_cy_1) LUT symbol "as/Madd__n0002_inst_lut2_011" (Output Signal = as/Madd__n0002_inst_lut2_0) LUT symbol "as/Madd__n0002_inst_lut2_110" (Output Signal = as/Madd__n0002_inst_lut2_1) The following RPM logic must use the same site due to RLOC origin usage: LUT symbol "z11" (Output Signal = CHOICE404) There are more than two function generators. Please correct the design constraints accordingly.
I have 'Use RLOC constraints' set in the 'Map properties' dialogue, and 'Allow Logic Optimisation Across Hierarchy' is unset in the same dialogue box.
Am I barking up the right tree, here ? Is this a "well-known" circumstance, or have I missed something obvious ?
Thanks for any help :-)