Why are there 2 clock supplies in Nios Apex board proto-connectors


I notice that each of the Prototype connectors in the Nios Apex Board offer two clock supplies ie. clk_OSC and clk_Apex? Is this to enable any connected peripheral access to the multiplied and unmultiplied clock signals used on board and by the Apex?

Also, please confirm this: The signal clk_Apex that is an output of the Apex FPGA is actually the clock signal used by the FPGA. If a clock multiplier is used in the FPGA, then this output would feedback the multiplied clock to the Clock Distributor on the board. The distributor then drives and distributes 5 copies of the fedback signal. Whereas, in the case where a clock multiplier is not used and the Apex uses the clock produced by the Oscillator, the output clk_Apex would essentially feedback the clk_OSC to the Distributor chip.

Is this accurate..?

Appreciate the help. Thanks

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