Power for Spartan 3

Be careful of the resistor values. We have used these parts and from my memory the LDO has a different reference voltage and hence resistor ratio to the switcher elements. Your 40mV could be resistor or reference tolerance have you checked those?

John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan3 Development Board.

"Peter Mendham" wrote in message news:e3v0va$brk$ snipped-for-privacy@dux.dundee.ac.uk...

I'll second that tolerance concern. I was surprised to find that the core voltage on some parts ('C5510 DSP) has a tolerance as low as +-50 mV making it about 3%. With two resistors and the innate tolerance of the part, that can be a tough spec to meet.

But I think the OP is saying the values selected provide a voltage 40 mV too high. I would suggest that you contact Xilinx support about this. They put a lot of things in app notes that may or may not be best for your design. Don't be afraid to change things, but it wouldn't hurt to contact them to ask why they picked what they picked.

Or are you talking about the TI app notes? Actually I don't see how you can say all three outputs are 40 mV too high when the 1.2 volt output does not use external resistors! The values in the TI data sheet (figure 1) produce about 2.54 volts, 3.29 volts and of course,

1.2 volts.

John Adair wrote:

John,

Thanks for your response. It think I have the resistor values correct, I've attempted to follow the app notes to the letter, anyway. Resistor and Vref tolerances is a good idea, I should have checked that before I posted. Having looked at them, it could possibly be the source of the

40mV. If it were required that near the lowest error tolerance bound the Vref was still not below the required value, this would seem make some sense. The only niggle is that the error bounds are relative (resistor/Vref), and this 40mV over-voltage doesn't change all that much from the 1.2V to the 3.3V supplies. The app notes don't seem to provide an explanation for this.

I have come up with two plans, one for a voltage close to spec, another for 40mV (approx) over. Unless I hear any different, I'll probably prototype with the former, and only use the latter if things go belly-up.

From your experience, do you have any other advice about using these devices?

Thanks,

-- Peter

John Adair wrote:

Yes, I am still on the drawing board at this point.

I am, I haven't found any Xilinx app notes about the part. Are there any?

Good point, my mistake. Sorry. Both Buck 2 and the LDO are approx 40mV too high.

I am indeed. I am probably being stupid, but using the values in all the TI example circuits (I have about 5 variations here) the Buck 2 potential divider uses values of 61K9 and 36K5 (or 319K and 365K). By equation 15 in the TI datasheet these values give a Vout of 3.343V. Similarly, for the LDO the value 2.545V. These are 43mV and 45mV over spec respectively. Now, it is extremely likely that I am either worrying about nothing, or being very stupid. Is this over-voltage specified deliberately, or is it simply a product of using nearest-fit resistor values? Or have I done my calculations badly? If you can clarify that for me I would be very grateful.

Best,

-- Peter

My design-time voltmeter (i.e. my calculator) is well calibrated :) I'm still on paper at this point. But thanks for the suggestion nevertheless.

-- Peter

Given the effect is on both supplies I would particularly look at anything common like the reference voltage or a common resistor value.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

"Peter Mendham" wrote in message news:e49ql2$pa6$ snipped-for-privacy@dux.dundee.ac.uk...

I would say that it is better to err slightly on the high side to compensate for IR drop between the regulator and the part. Once you build the prototype you can measure the actual drop (both ground and high sides) and tweak your values accordingly.

I have used the TPS75003 in a ceramic capacitor configuration, because tantalum and small electrolytic capacitors are prohibited in our applications. In this case the divider network has to be designed differently to provide AC feedback from the switch. I asked TI about this, and they recommended that I follow the guidance in the TPS64200 datasheet (see figure 27 and associated discussion). This has worked well.

================================

Greg Neff VP Engineering

*Microsym* Computers Inc. snipped-for-privacy@guesswhichwordgoeshere.com

The error on 3.3V is 1.3%, which will be nearest fit resistor values. Normally, simplest design uses two resistors, and it is hard to nail a value under 1% with available values.

If this is loosing you sleep, then move to a 3 resistor design, and also be prepared to pay for resistors under 1% tolerance.

In a real design, you should measure/verify the voltage AT THE DEVICE, which means a few mV high allows for some trace/choke IR drop.

Also check the dynamic power changes, and output impedance of your regulators, as that is another error source.

-jg

At the moment, the design is slated as having a three resistor design. I figured that was the most flexible in terms of layout. If my paranoia is unfounded then we'll throw in a zero-ohm resistor and go back to two.

OK, I've spec'd an alternative which measures high by about the same as the TI reference designs and I'll try both on the prototype, see how they come out.

Thanks, for the advice, it is much appreciated.

-- Peter

Thanks, I will do. I have two alternative designs each with three or two resistors, so I'm laying out three and will do playing at the prototyping stage.

Thanks for the advice, I'll take a look at that datasheet also.

-- Peter

I don't know about stupid, but I didn't see the equations... :) I just used the stated feedback voltage and the resistor ratios to get my numbers. I don't know why your numbers are different from mine. What equations did you use? I used Vf * (R1+R2/R2), where R1 is the resistor that connects to the output voltage and R2 is the resistor that connects to ground.

Regardless, I would not worry about 40 mV on either of these supplies.

Ahhh, thanks to your persistence, I have spotted what I was missing. Yes, indeed, there was a certain amount of stupidity involved, I'd be the first to admit. The datasheet states a value of Vfb of 1.24V next to equation 15. Foolishly, I used this, instead of 1.22V as stated earlier in the datasheet (which I've only just noticed). I assume that the 1.24V is the upper tolerance bound 1.22V+2% ~ 1.24V. I'm not quite sure why, it seems a little arbitrary to me to pick one boundary for the example calculation. Thoughts?

-- Peter

Hopefully a 1% zero ohm resistor :-)

Sorry! Martin

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt

My first thought was a datasheet error, and there it is. Download the latest version of the datasheet. The equation has been corrected.

I remember a TI datasheet error for a voltage supervisor, where the timing capacitor equation produced a capacitance value of several Farads.

I wish TI put revision histories in their documents. It would be nice to know what else changed...

================================

Greg Neff VP Engineering

*Microsym* Computers Inc. snipped-for-privacy@guesswhichwordgoeshere.com

Hooray, it's not my fault :)

Mind you, I evidently should have checked for errata. Thanks, Greg.

-- Peter