I'm new to Spartan-3, before I only worked on the legacy XC6216 FPGA. I am trying to port a university project over to a modern FPGA platform.
I assume that the full details of the Spartan-3 bitstream are not published beyond what is described in XApp452 (XC6216 bitstream was fully published).
Also I assume that it is possible to damage the FPGA using invalid bitstreams (as opposed to the XC6216).
I want to generate a placed & routed design using my own custom algorithms and then upload it to the Spartan-3, without resorting to PAR tools and such.
At what point would I have to enter the workflow? Convert my design to NCD files? (Most likely, the NCD format is closed as well?)
This seems to be just what I need. I already tried it. However, I definitely need to speed this up somewhat.
It looks like I first have to re-convert the XDL-File to NCD using xdl.exe, and only then use bitgen. Or do you mean that I can somehow configure bitgen to accept XDL-Files?
I just have to go from XDL-code to bitstream real fast. Preferably on-chip. Have you heard of ways to use Xilinx tools like "xdl" and "bitgen" on the FPGA itself?
No. These are large programs that depend on complex database files that are part of your sw instalation.
Sorry for the less than clear answer I gave. I wrote
What I should have written is this:
1) create a test design with maybe the stuff you know wont change and also some example stuff that uses all the I/Os you plan to use. Do this using the normal tool flow, such as VHDL/Verilog ->
synthesis -> P&R -> Timing analysis -> bitgen. Make sure this works, and the I/Os you care about wiggle.
2) Take the NCD from the previous step, and run through XDL. Read the result very carefully, maybe comparing what you read with the view of the same design in fpgaeditor. Keep reading until you think you understand XDL syntax and all the many flavors of how it describes your design. There is no customer documentation that explains this. All XDL users end up going through this reverse engineering step.
3) Once you think you know what is going on, make a trivial change to the ascii from XDL, and convert it back to NCD, and load it into fpgaeditor. See if you got it right. If you did, try something more adventurous. Repeat till you feel confident.
4) Take the ascii of your test design as your baseline. Make the changes you want. Convert to NCD with XDL, and convert NCD to a bitstream with bitgen.
5) Repeat step 4 as you pursue your research of algorithms. Have fun.
=================== Philip Freidin snipped-for-privacy@fpga-faq.org Host for
That does the job. However, I have a few concerns:
- I cannot implement XDL compilation on an FPGA. Maybe JBits would be an alternative for the Virtex-II. Do you know whether JBits can be run under the JOP java core?
- XDL is depreciated, as is JBits. Which technology do you think will be around longer? Which one to prefer?
- There used to be XDL documentation in Xilinx/help/data/xdl.html, according to postings in this group. This is definitely no longer true for the WebPack 7.1. Does anyone have a copy of this xdl.html and mail it to me? Or is it available somewhere else? (Not at xilinx.com as far as I can see)
"Tobias Weihmann" schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...
it looks like the XDL will be around for a while - JBits was never an option at all, it was always, 'maybe.. oneday..' but the day never did arrive
XDL is not advertized much, true but its still is part of ISE 7.x well it the .NCD files created with it are not compatible with ISE 7.x (and with no other version as well) and the Answer Record on this is dated ISE 6.3 and provides no solutions.
xdl.html was in the 6.3 at least, in 7.1 it seems to be vanished.
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