circular buffer(its urgent)

I don't know what you mean by "logical address" and "physical address" in your context.

But a circular address generator for me would count

so

-------< CUT >---------- signal rst:std_logic; signal clk:std_logic; signal cnt:std_logic_vector(9 downto 0);

process(clk) begin if rising_edge(clk) then if rst='1' then cnt '0'); else if (cnt = "1110111111") then cnt '0'); else cnt ----------

Note that if you don't need it to count upwards (i.e. just for a FIFO without direct access), the downwards version might be smaller.

-------< CUT >---------- signal rst:std_logic; signal clk:std_logic; signal cnt:std_logic_vector(9 downto 0); signal cnt_n:std_logic_vector(10 downto 0);

cnt_n