I want to map an RTL which synthesize on Synopsys Design compiler on FPGA (Synplify is the tool and Xlinx is the FPGA I want to use for mapping)
The issue is that this unit uses Synopsys Designware components (FIFO controller, counters and 8b10b enc / dec)
What is tyhe safest and fastest path to migrate this design on Sinplify?
Thanks in advance