I want to map an RTL which synthesize on Synopsys Design compiler on FPGA (Synplify is the tool and Xlinx is the FPGA I want to use for mapping)
The issue is that this unit uses Synopsys Designware components (FIFO controller, counters and 8b10b enc / dec)
What is tyhe safest and fastest path to migrate this design on Sinplify?
Thanks in advance
Hi Andy,
Xilinx offers a rich suite of LogiCore IP which are delivered through the Xilinx CORE Generator, and included with your ISE installation. You can then instantiate the generated cores into your design. We have solutions for all of the elements you mention. To access them from CORE Generator:
Basic Elements -> Counters -> Binary Counter Communication & Networking -> Building Blocks -> Decode 8b/10b -> Encode 8b/10b Memories and Storage Elements -> FIFOs -> Fifo Generator
You can find more information on all of the IP available from our IP Center:
I hope this helps- -Stacey
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