Xilinx Virtex II Output Register

Jan 06, 2004 2 Replies
J

I have a input signal thats get registered and then outputed on another signal (pad) One register delay. I would like the Output register to used instead of the Input register. I am using Xilinx ISE, VHDL and a Virtex II device. Everytime I implement the Input register is used, how do I use the Output register. I am trying to improve the clock to pad time.



Thanks John C


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B

Set IOB=FALSE on the input instance name and IOB=TRUE on the output instance name, or use the primitives IBUF for the input buffer and OFDXI for the output.

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B

John,

Since this is a Virtex-II device and you already have IOB FFs enabled, all you need to do is add a BEL constraint to OFF1 or OFF2:

INST "FF_Name" BEL = OFF1 ;

IOB BEL constraints aren't supported for architectures older than Virtex-II, so for a Virtex-E design, one of the following map constraints could be used:

  1. Give FF and output pad the same BLKNM constraint.
  2. Give FF and output pad the same LOC constraint.
  3. Apply a KEEP constraint to the FF D input net, assuming fanout of

  5. Regards, Bret

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