> Hi,
>
> I have a serial bus coming in a Virtex II -5 in LVDS format at 80 MHZ
> with 3 data in parallel. The data change on the falling edge of the
> clock. The problem is that the clock is present only when data is
> transmitted (no DCM possible) and the pads used for the clock does not
> allow the use of a bufgp without an important routing delay. I am
> using the MAXSKEW constraint on the received clock and the best I can
> get is 450 ps (I can not use the local clock resources described in
> xapp609). This clock goes to approximately 40 FFs. I have, on this
> clock domain, among other things, a shift register so I have a FF to
> FF path. When having the min skew of 450 ps parts of the shift
> register are implemented in the same CLB so the output of a FF goes
> through the local routing matrix of the CLB and back to the input of a
> FF in the same CLB : I believe it must be the shortest and quickest
> path to go from one FF to another. My problem is that I wonder if the
> skew I have will always be smaller than the clock_to_out + prop_delay
> : I believe the max values are ok but what about typical ?
>
> Thank you.
>
> J.F. Hasson