DDR capabilities of a Virtex II device


I have a Virtex II -5 and I would like to use the DDR registers in the IOBs. I read a few application notes involving these registers and it is always sais that the skew between two signals ouptut from DDR registers, especially if the IOBs are in the same bank, is negligible. What is negligible ? What if the IOBs are not in the same bank ? I read in a previous post that a reasonable 30% tracking could be expected between two IOBs but that this tracking was much much better when a same category of the device was considered. What is this tracking downto when considering IOBs ?



Reply to
jean-francois hasson
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JF (is this a new thing in France? All of the Jean-whatevers going by their intitals? Seems to be popular for ex-patriot French Engineers here in silicon valley to suddenly go from Jean-Louis or Jean-Reynard to JL or JR .... it isn't Texas you know...and I didn't think the French were too enamored of Bush....)

The skew from one IOB to an adjacent IOB is less than 20 ps. The skew across the entire top, bottom, left or right edges, can be found in the source synchronous section of the data sheet, or by probing the timing of the paths in FPGA Editor.

If you use a flip chip package, we also have "flight time" maps of the delay from the pad to the pin, so that you may design your pcb to remove this skew as well.

For designs using DDR avbove 600 Mbs, one has to use both the IOB to IOB skew, and the pad to pin flight time information to keep your timing budget as tight as possible.

Bon Chance,

Aust> Hi,

Reply to
Austin Lesea

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