Interesting Simulation Problem

In LTSpice and in gEDA the stored data is all human readable.

RAW files in LTSpice are just huge lists of voltages - one voltage for every node in the circuit at any specific instant.

Machine searching a RAW file at a specific instant for a voltage that wasn't Vcc or Gnd doesn't sound too difficult for anybody who can use awk or any similar file-seaching engine.

Searching for a voltage that was "significantly" different from Vcc or Gnd might take a Basic/Pascal/C/Fortran program and you'd have to define "significant".

Create a phony-baloney OR gate with 10,000 inputs.

Can't you take the NMOS and PMOS models and incorporate a small current source between gate and source that would normally turn the FET on if the gate was allowed to float?

I think the answer is to use the built-in gmin node loading, but with a twist... still pondering ;-) ...Jim Thompson

Afterthought. LTSpice RAW files don't just include all the node voltages at every instant, but also all the currents between connected nodes - since nodes are connected by components, these are identified with the components rather than with the nodes.

Any circuit analysis program has to calculate both currents and voltages. They don't have to store them - and you can make LTSpice selective about what it stores - and not everybody stores them in a well-defined and easily searchable format. LTSpice is good like that, and the gEDA programs had the same philosophy.

If Jim searched the currents he'd get the currents he's actually worried about, rather than the floating nodes that make the currents possible.

And my list of possible programming languages should have included LISP. It was - after all - designed as a list-processing language.

For static CMOS logic, there shouldn't be any floating nodes. Thus the number of nodes to inspect is substantially less than the original problem states.

Thus the analysis needs to be limited to the analog circuitry and where analog interfaces with digital. Because spice can do the impossible, i.e. for example sit in a metastable state, the only solution is to inspect the circuitry by hand (OK, actually brain). So you insure all logic inputs are driven to rails. For the analog circuitry, you need to look at everything.

BTW, your layout verification program should flag any gate that isn't connected to both a P and N mosfet. [The assumption here is you need both sexes of fets to insure the gate is drivien to a rail.] A flagged transistor isn't necessarily a problem, but it is something to look at. The analog portions of the chip will have flagged devices.

I'm probably stating the obvious here, but in general you should be on the lookout for circuits that can trap charge when the supply rail(s) is/are grounded. For example, on a single supply chip, you would insure that each cap has a parasitic diode to the positive rail so when that rail is grounded, the cap is discharged.

Not exactly on the same topic, but somewhat related, many a board designer has made what I consider to be flaky products by using pfet pass devices to kill the power to a part of the board they want to power down, even if you provide a shutdown pin on all the chips.

The reason they use the pfet pass device is they see the leakage spec on each chip, which is generally way higher than the chip will actually leak. The leakage specs are high because to measure the leakage current is a time consuming test. The problem with the pfet pass device is you might provide a means to latch up a chip when you turn on the pass device.

Can you run your SPICE file through a perl script or similar that appends a current source to every gate?

Then set the thing to sleep mode, turn all the current sources on, and see if any voltages rise.

Alternately (if the thing isn't already done), build it up with subcircuits that include the current sources that can be turned on.

I don't think you want the current sources on all the time -- that would mess your simulation up at other times -- you just want the current sources on when you're verifying that sleep is really sleep.

Come to think of it -- you want to do a run with each current source turned on INDIVIDUALLY. All 30000 of them. Ho boy -- you are getting paid by the hour, right?

How much do you pay me for the answer? :-) Search a bit harder, it's a matter of just 5 seconds...

The way LTspice performs, I can't imagine it trying 30k nodes.

Jamie

I did indeed think of a script, actually some netlist automation thru UltraEdit.

Instead of current sources I was going to use large value resistors to mid-rail (since all "sleep" devices should have their gates at rail or GND), then I realized that can be automated in Spice... set gmin (a resistor from all nodes to node 0/zero) high, then run the circuit on split rails VDDnew = VDD/2, "GND"=-VDD/2, and look for zero volts.

Pay? Most of the schemes I post here are for my own edification... just had the problem come up in a small cell, maybe a few hundred nodes, voltages easily observable all at once; but then I got to fretting ;-) ...Jim Thompson

It's hard to imagine an analog circuit that needs 20,000 transistors.

It's like the windows OS, layer ontop of layer.

Like the windows OS, how much of that 20K transistors are actually needed? I smell a lot of copy and paste from pre-existing projects, bringing with it, lard!

Jamie

It's a system... aka SOC. But I acknowledge that's well beyond your mental capability >:-} ...Jim Thompson

Unless it has a thousand wirebonds, what can all those analog transistors do?

Jamie/Maynard, Displaying his fundamental ignorance. ...Jim Thompson

I'm having trouble understanding this open display of your ignorance of complex integrated circuits?? ...Jim Thompson

You're having trouble modeling a neon bulb, too.

Nope. You missed it. As usual >:-} ...Jim Thompson