Hi, I'm writing this newsgroup because i'm facing a stange problem while simulating a ppc system for V2PRO generated with EDK 3.2. Indeed, the PPC doesn't start correctly. I've generated a behavioural simulation model with EDK wich I'm including in a top level and then in a bench, all of them in VHDL. modelsim seems to load correctly the swift model and the simulation starts correctly. After reset with a proc_sys_reset instance, the ppc model issues the correct adress to the i-ocm at boot (FFFFFFFC translated to the iocm adress). The ocm returns an opcode and the ppc stalls, the adress doesn't change and the instruction doesn't seem to be executed.
What kind of problem could it be ?
Did I forget something in my system.mhs file ? I've started from a generated one which I modified by hand. The original had a system_dcm which I suppressed because I had trouble to simulate it. Did I forget something ?
Thanks a lot for your help
Note : i'm using modelsim on a sun workstation
For your info, here is the system.mhs .... # ############################################################################# # Created by Base System Builder Wizard for Xilinx EDK 6.2 Build EDK_Gm.11 # Modified by hand # Target Board: Avnet Avnet Virtex-II Pro Development Board Rev 1.0 # Family: virtex2p # Device: XC2VP7 # Package: FF896 # Speed Grade: -5 # Processor: PPC 405 # Processor clock frequency: 100 MHz # Bus clock frequency: 100 MHz # Debug interface: No Debug
PARAMETER VERSION = 2.1.0 PORT RS232_TX = RS232_TX, DIR = O PORT RS232_RX = RS232_RX, DIR = I PORT SDRAM_RASn = SDRAM_RASn, DIR = O PORT SDRAM_DQ = SDRAM_DQ, VEC = [0:31], DIR = IO PORT SDRAM_Clk = SDRAM_Clk, DIR = O PORT SDRAM_CSn = SDRAM_CSn, DIR = O PORT SDRAM_CASn = SDRAM_CASn, DIR = O PORT SDRAM_BankAddr = SDRAM_BankAddr, VEC = [0:1], DIR = O PORT SDRAM_Addr = SDRAM_Addr, VEC = [0:11], DIR = O PORT SDRAM_DQM = SDRAM_DQM, VEC = [0:3], DIR = O PORT SDRAM_WEn = SDRAM_WEn, DIR = O PORT SDRAM_CKE = SDRAM_CKE, DIR = O PORT SRAM_A = SRAM_A, VEC = [0:31], DIR = O PORT SRAM_DQ = SRAM_DQ, VEC = [0:31], DIR = IO PORT SRAM_CEN = SRAM_CEN, VEC = [0:1], DIR = O PORT SRAM_OEN = SRAM_OEN, VEC = [0:1], DIR = O PORT SRAM_WEN = SRAM_WEN, DIR = O PORT SRAM_QWEN = SRAM_QWEN, VEC = [0:3], DIR = O PORT SRAM_BEN = SRAM_BEN, VEC = [0:3], DIR = O PORT SRAM_RPN = SRAM_RPN, DIR = O PORT SRAM_CE = SRAM_CE, VEC = [0:1], DIR = O PORT SRAM_ADV_LDN = SRAM_ADV_LDN, DIR = O PORT SRAM_LBON = SRAM_LBON, DIR = O PORT SRAM_CKEN = SRAM_CKEN, DIR = O PORT SRAM_RNW = SRAM_RNW, DIR = O PORT sys_irq = sys_irq, VEC = [0:0], DIR = I, LEVEL=HIGH, SIGIS = INTERRUPT PORT sys_clk = sys_clk_s, DIR = IN, SIGIS = CLK PORT sys_rst = sys_rst_s, DIR = IN PORT SDRAM_Clk_in = SDRAM_Clk_in, DIR = IN BEGIN ppc405 PARAMETER INSTANCE = ppc405_0 PARAMETER HW_VER = 2.00.c BUS_INTERFACE DPLB = plb BUS_INTERFACE IPLB = plb BUS_INTERFACE DSOCM = docm BUS_INTERFACE ISOCM = iocm PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ PORT CPMC405JTAGCLKEN = net_vcc PORT MCPPCRST = net_vcc PORT BRAMDSOCMCLK = sys_clk_s PORT CPMC405CPUCLKEN = net_vcc PORT PLBCLK = sys_clk_s PORT EICC405EXTINPUTIRQ = opb_intc_0_irq PORT EICC405CRITINPUTIRQ = net_gnd PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ PORT RSTC405RESETCHIP = RSTC405RESETCHIP PORT CPMC405TIMERCLKEN = net_vcc PORT RSTC405RESETCORE = RSTC405RESETCORE PORT RSTC405RESETSYS = RSTC405RESETSYS PORT CPMC405CORECLKINACTIVE = net_gnd PORT CPMC405TIMERTICK = net_vcc PORT BRAMISOCMCLK = sys_clk_s PORT CPMC405CLOCK = sys_clk_s END BEGIN proc_sys_reset PARAMETER INSTANCE = reset_block PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Rstc405resetsys = RSTC405RESETSYS PORT Rstc405resetcore = RSTC405RESETCORE PORT Rstc405resetchip = RSTC405RESETCHIP PORT Bus_Struct_Reset = sys_bus_reset PORT Chip_Reset_Req = C405RSTCHIPRESETREQ PORT System_Reset_Req = C405RSTSYSRESETREQ PORT Ext_Reset_In = sys_rst_s PORT Slowest_sync_clk = sys_clk_s PORT Core_Reset_Req = C405RSTCORERESETREQ PORT Dcm_locked = net_vcc END BEGIN isocm_v10 PARAMETER INSTANCE = iocm PARAMETER HW_VER = 1.00.b PARAMETER C_ISCNTLVALUE = 0x85 PORT sys_rst = sys_bus_reset PORT ISOCM_Clk = sys_clk_s END BEGIN isbram_if_cntlr PARAMETER INSTANCE = iocm_cntlr PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0xfffff000 PARAMETER C_HIGHADDR = 0xffffffff BUS_INTERFACE DCR_WRITE_PORT = isocm_porta BUS_INTERFACE INSTRN_READ_PORT = isocm_portb BUS_INTERFACE ISOCM = iocm END BEGIN bram_block PARAMETER INSTANCE = isocm_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = isocm_porta BUS_INTERFACE PORTB = isocm_portb END BEGIN dsocm_v10 PARAMETER INSTANCE = docm PARAMETER HW_VER = 1.00.b PARAMETER C_DSCNTLVALUE = 0x85 PORT DSOCM_Clk = sys_clk_s PORT sys_rst = sys_bus_reset END BEGIN dsbram_if_cntlr PARAMETER INSTANCE = docm_cntlr PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0xffff0000 PARAMETER C_HIGHADDR = 0xffff1fff BUS_INTERFACE PORTA = dsocm_porta BUS_INTERFACE DSOCM = docm END BEGIN bram_block PARAMETER INSTANCE = dsocm_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = dsocm_porta END BEGIN plb_v34 PARAMETER INSTANCE = plb PARAMETER HW_VER = 1.01.a PARAMETER C_DCR_INTFCE = 0 PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_bus_reset PORT PLB_Clk = sys_clk_s END BEGIN opb_v20 PARAMETER INSTANCE = opb PARAMETER HW_VER = 1.10.b PARAMETER C_EXT_RESET_HIGH = 1 PORT OPB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN plb2opb_bridge PARAMETER INSTANCE = plb2opb PARAMETER HW_VER = 1.00.b PARAMETER C_DCR_INTFCE = 0 PARAMETER C_NUM_ADDR_RNG = 2 PARAMETER C_RNG0_BASEADDR = 0x00000000 PARAMETER C_RNG0_HIGHADDR = 0x1fffffff PARAMETER C_RNG1_BASEADDR = 0x20000000 PARAMETER C_RNG1_HIGHADDR = 0x2000ffff BUS_INTERFACE SPLB = plb BUS_INTERFACE MOPB = opb PORT OPB_Clk = sys_clk_s PORT PLB_Clk = sys_clk_s END BEGIN opb_uartlite PARAMETER INSTANCE = RS232 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x20000000 PARAMETER C_HIGHADDR = 0x200000ff PARAMETER C_BAUDRATE = 115200 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_CLK_FREQ = 66000000 BUS_INTERFACE SOPB = opb PORT TX = RS232_TX PORT OPB_Clk = sys_clk_s PORT RX = RS232_RX END BEGIN opb_sdram PARAMETER INSTANCE = opb_sdram_0 PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0x10000000 PARAMETER C_HIGHADDR = 0x11ffffff PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 0 PARAMETER C_SDRAM_TMRD = 2 PARAMETER C_SDRAM_TCCD = 1 PARAMETER C_SDRAM_TRAS = 50000 PARAMETER C_SDRAM_TRC = 100000 PARAMETER C_SDRAM_TRFC = 100000 PARAMETER C_SDRAM_TRCD = 20000 PARAMETER C_SDRAM_TRRD = 20000 PARAMETER C_SDRAM_TRP = 20000 PARAMETER C_SDRAM_TREF = 64 PARAMETER C_SDRAM_CAS_LAT = 2 PARAMETER C_SDRAM_COL_AWIDTH = 9 PARAMETER C_SDRAM_BANK_AWIDTH = 2 PARAMETER C_SDRAM_AWIDTH = 12 PARAMETER C_SDRAM_DWIDTH = 32 PARAMETER C_OPB_CLK_PERIOD_PS = 15000 BUS_INTERFACE SOPB = opb PORT SDRAM_RASn = SDRAM_RASn PORT SDRAM_DQ = SDRAM_DQ PORT SDRAM_Clk = SDRAM_Clk PORT SDRAM_CSn = SDRAM_CSn PORT SDRAM_CLK_in = sys_clk_s PORT SDRAM_CASn = SDRAM_CASn PORT SDRAM_BankAddr = SDRAM_BankAddr PORT SDRAM_Addr = SDRAM_Addr PORT SDRAM_DQM = SDRAM_DQM PORT OPB_Clk = sys_clk_s PORT SDRAM_WEn = SDRAM_WEn PORT SDRAM_CKE = SDRAM_CKE END BEGIN plb_bram_if_cntlr PARAMETER INSTANCE = plb_bram_if_cntlr_1 PARAMETER HW_VER = 1.00.a PARAMETER c_plb_clk_period_ps = 10000 PARAMETER c_baseaddr = 0x30010000 PARAMETER c_highaddr = 0x30013fff BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port BUS_INTERFACE SPLB = plb PORT PLB_Clk = sys_clk_s END BEGIN bram_block PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port END BEGIN opb_emc PARAMETER INSTANCE = opb_emc_0 PARAMETER HW_VER = 1.10.b PARAMETER C_OPB_CLK_PERIOD_PS = 15000 PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x000001ff PARAMETER C_NUM_BANKS_MEM = 2 PARAMETER C_MEM0_BASEADDR = 0x00100000 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_1 = 0 PARAMETER C_SYNCH_MEM_0 = 0 PARAMETER C_SYNCH_PIPEDELAY_0 = 2 PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 150000 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 55000 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 70000 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 150000 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 55000 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 15000 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 35000 PARAMETER C_SYNCH_MEM_1 = 0 PARAMETER C_SYNCH_PIPEDELAY_1 = 2 PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_1 = 150000 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_1 = 55000 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_1 = 70000 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_1 = 155000 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_1 = 55000 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_1 = 15000 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_1 = 35000 BUS_INTERFACE SOPB = opb PORT Mem_A = SRAM_A PORT Mem_DQ = SRAM_DQ PORT Mem_CEN = SRAM_CEN PORT Mem_OEN = SRAM_OEN PORT Mem_WEN = SRAM_WEN PORT Mem_QWEN = SRAM_QWEN PORT Mem_BEN = SRAM_BEN PORT Mem_RPN = SRAM_RPN PORT Mem_CE = SRAM_CE PORT Mem_ADV_LDN = SRAM_ADV_LDN PORT Mem_LBON = SRAM_LBON PORT Mem_CKEN = SRAM_CKEN PORT Mem_RNW = SRAM_RNW END BEGIN opb_intc PARAMETER INSTANCE = opb_intc_0 PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0x03000000 PARAMETER C_HIGHADDR = 0x030000ff BUS_INTERFACE SOPB = opb PORT Intr = sys_irq PORT Irq = opb_intc_0_irq END