I would like to write a testbench in VHDL using constrained random values and transactions. Are there any free packages that people know about that do this sort of thing?


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For constrained randoms, you'll find one here...

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Hi, interesting link.

So, if we take VHDL, expand it with some ADA for OOP-features and add these packages (maybe after some improvements) and not to forget some PSL like assertions, all bundled in a new standard, what do we get?


Looks like there is some need for it... ;-)

Have a nice Simulation Eilert

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YES! (Ada not ADA by the way) Ada does at last seem to be increasing in popularity, and as of Ada-2005 has gained flexibility over the 1995 revision (although VHDL-2008 beat Ada-2012 to conditional expressions :-)

And Ada has fixed-point types with user-defined ranges built in, so it should be ideal for algorithm accuracy simulation before conversion to hardware.

I'd like to go further with SystemVHDL though, and exploit the similarities between the SPARK subset* of Ada, and the synthesisable subset of VHDL.

SPARK is not regarded as a subset but a new language with annotations, effectively contracts, in the form of Ada comments, such that any SPARK program is a fully compliant Ada program. It has restrictions imposed on it, such that a SPARK program is completely unambiguous, and can be formally proven to be error-free (e.g. guaranteed never to overflow an integer).

Now, firstly that approach to design verification appeals greatly to the hardware engineer in me.

But secondly, many of the restrictions SPARK places on Ada look remarkably like the restrictions you have to employ on VHDL if you want it to synthesise. For example, no dynamic storage allocation. SPARK goes a little further than most synthesis tools by prohibiting recursion, but the only synthesisable recursion I can recall is that cute "tree of gates" example (which most synth optimisers will generate from a linear chain of gates anyway).

It's not a complete match, but close enough to make me speculate that there is some deep-seated commonality between the principles of provability (in finite time) and synthesisability (to finite hardware resource).

So I'm looking for Ada for OO testbenches and fixed point arithmetic for algorithm simulation, and SPARK-HDL, VHDL with SPARK annotations to formally prove as much as possible about the synthesisable design.

- Brian

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Brian Drummond
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I must say that SystemVHDL appeals to me also.

As an aside, a few years ago, for testbenching purposes I required some string/character functions such as 'is_whitespace' and found them in an Ada function package that ModelSim compiled with minimal changes...

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