Generate errors on I2C link to test it


The I2C communication between my master and slave seems to work perfectly. I simulated a SDA line cut and put it back. The system recovered. Same thing for the SCL.

Though, I have a special situation where my slave does not recover as expected. It returns NOT ACK instead of ACK after it recovers from I2C failure.

I tried to simulate the whole thing when cutting the SDA and SCL, but I am too slow and really needs to generate the error within the transmission.

Is there a tool, software or techniques to fully test the I2C protocol and transmission? I know my serial link cable catch lots of noise, and seems to be affected once a while. It is REALLY hard to generate the problem. In fact, so far, I failed all the time.

Thanks for your help

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You said you want to test it in simulation. Why wouldn't you be able to do what you want in simulation? I assume you really mean you are trying to test your actual system.

What is acting as the master? If it is an MCU, you should be able to write some code that will take the port out of I2C mode in the middle of a transmission and generate any sort of glitch you desire. Or you can add a third party to the bus and have it disrupt transmission by pulling down on one of the signals when triggered, either by you or when it detects something in the transaction.

If you are doing this in an FPGA then you should be able to implement any sort of test function that suits the need.


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You were right, I wanted to generate errors on my actual system (don't have simulation tool)

My problem right now is I don't have the control over the slave code. But like you suggest, I will maybe try two things:

  1. Build a board where my I2C link will be broke down to switches. I will be able to cut the SCL and/or SDA OR pull them down to the ground.
  2. The other solution is to build another board with MCU that generates noise or glitches to those lines (SCL + SDA)

Do you have some names for third party tools that can do what I want?

Thanks Rick

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Is this likely to happen in a *real* system? I.e., are the conductors "in foil"?

How is this different from the above scenario?

Do you have control over master *and* slave? (i.e., can you alter the data rate to something convenient -- like DC?)

Do you *know*/suspect what the problem is and simply need a way of reliably reproducing the conditions under which it occurs? Or, do you know there is *a* problem and are now trying to determine what the exact conditions are that cause it to manifest?

What happens in the system (hardware and software) when the "problem" occurs? Is there anything that could be used as a suitable trigger even (even ex post factum) for you to capture the conditions which led to the error?

If you want to generate a particular SCL/SDA "signal sequence", you could use a bit of custom code (that you write) to twiddle two signal lines directly (this is most flexible). If this isn't fast enough, you could design a simple sequencer that pushes a programmed pattern onto the signal lines.

If the problem is not *directly* reproducible by a particular sequencing of SCL/SDA (i.e., if there is any "state" involved), then you will need a better handle on what drives that state before you can reproduce it *and* the signal conditions.

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D Yuniskis





No, I don't know of any tools that will do this. I would think the second solution would be pretty easy. Software monitoring of the two signals would allow the MCU to pick any point in the transmission to introduce a glitch by pulling down on the line when it should be high. You would not need to build any hardware other than figuring out how to connect the debugger to your I2C signals.


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