Hi @ all,
I am trying to use the Quartus SignalTap Analyzer.
Maybe someone can help me with my problem:
In the current state of my design test I have programmed my device. The receiving logic does not run yet because there is no incoming data traffic yet so that no IDLE-->Low transition is recognized. (Start of packet).
And yet I would like to know whether the PLL does generate the clocks correctly (PLL inclock:30MHz outclocks: c0 48MHz c1 : 90MHz, e0: 90MHz (external use)
Because of the fine package and the used board layers it is almost impossible to measure the clocks externally with an oszilloscope.
So the question is how to make the clocks visible with the SignalTap Analyzer. As I read in the application note it is said that clocks cannot be monitored.
But I cannot imagine that such a basic condition for a synchronous design cannot be captured.
What possibilities do I have ?
Thank you for your help.
Kind regards
André