I was using the nice feature of Verilog 2001, constant functions, to specify port widths. Some of my constant functions called other constant functions. Synplify had no problem with this. However, Modelsim won't allow me to call constant functions from within constant functions, so I have to embed the functions so there is only a single function call. Weak. Is that part of the standard or just a Modelsim shortcoming?
-Kevin