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Single ended LVDS into FPGA

Some food fo thought:

I'm working on a new design in which I need to bring 64 LVDS (250Mbps each/ 125MHz fmax) lines into a Spartan3 FPGA. The distance between the source and the FPGA is less than 2" / 5cm. Ofcourse there is a solid ground plane underneath the signals (the board will have at least 4 layers).

I'm wondering if I can save a lot of pins if I feed the LVDS signals single ended into the FPGA (terminate the pair close to the FPGA and leave one end dangling). I could bias the Vref pins on the FPGA to the centre point of the LVDS signal. If I set the input pin type to GTL it should work on paper. The LVDS signal has enough swing to exceed the minimum signal amplitude.

Anyone ever tried this?

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Reply to
Nico Coesel
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You have no guarantee on the common mode voltage so this is a risky approach. But there is no reason for that. Just use one of the existing single ended high speed low swing signaling standards. (HSTL, SSTL, whatever) Also, you should use internal termination.

Kolja Sulimma

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Reply to
Kolja

The thing that would concern me is how to guarantee that VREF is held at the centerpoint (common mode) of the signal swing. If you were only dealing with one pair then you get tricky and extract the common-mode point from that pair - assuming that the signal was always transitioning. Knowing that you've selected the proper sampling point for all 64 signal will take a leap of faith because I don't think that the common-mode points are guaranteed that accurately.

LVDS does take a lot of pins, but its advantages (low power, low SSO footprint, simple termination scheme), in my experience, have always outweighed the I/O count requirements.

Bob

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Reply to
BobW

The datasheet of the source chip specifies that. I more or less assume the source chip has the same centerpoint on all outputs.

IMHO you don't need a signal that is always toggling. If you connect a resistor to each leg of the pair and a capacitor to ground (resistor divider between the two legs) then the voltage across the capacitor should be the centre voltage no matter what the LVDS signal looks like.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn\'t fit, use a bigger hammer!"
--------------------------------------------------------------
Reply to
Nico Coesel

Ahhh, yes. Silly me.

I hope this works out for you. I suspect it will if you adapt VREF to the true centerpoint of one of the signals and if all the driver's common mode points stay fairly close to each other.

If one of those pairs is a forwarded clock, and if you decide to do the VREF adapt technique, then I wouldn't use the clock line for that function. LVDS is not intrinsically source terminated (it's high impedance drive [current source]). So, if you get any type of end reflection it will eventually come back toward that receiver. Data lines are somewhat forgiving. Clock lines are like women.

Bob

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Reply to
BobW

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You should consider running both halves of each pair up to the Spartan 3 and terminate with 100 ohms differential near the pin. This gets rid of the reflection issue although you end up with more routing. It also addresses another issue found with most LVDS drivers that I've come across. They are designed to run into a 100 ohm differential load. Very often they won't work properly without the load. What I see is that the signal swing increases significantly without the load, especially at low frequencies. Then the switching delay increases with the increased swing. So if you have a data bit that toggles on random clock edges, the clock to output delay through the LVDS device will be longer after it has sat at the same value for more than one clock period than on edges where it toggled on the previous cycle. This second issue could be handled with the termination resistor near the source, but once you have the extra parts and routing, it seems reasonable to put the resistor where it gives the best signal integrity.

Regards, Gabor

Reply to
gabor

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