I'm working on a Virtex 5 project containing a 13-stage pipeline clocked at200 MHz. The data path gets quite wide in the latter stages; but only 11% of available slices are used; so the FPGA is relatively empty. Every other step in the build process rips through quickly, except the above named MAP stage, which accounts for 98% of total build time. Routing is over in a flash, and the result meets timing. I would like to reduce the build time and I was wondering how to go about it. One idea was to create LOC constraints on logic, perhaps based on where the tools themselves placed it after a previous optimization run. Any other suggestions?