SRAM to be able to read/write Micron SDRAM

Hello all,

I had psted this question earlier but havent got any response yet... I was wondering if the questions I asked made any sense (or) were they just out of the way... So again, I have the Micron SDRAM Verilog code and I need to make SRAM read/write the SDRAM... Obviosuly, the SRAM shold maintain its own functionality (i.e. it itself can be read/written).

The questions I have are:

(1) Should my SRAM just issue Read/Write command to SDRAM Controller and then it will do the rest i.e. Read/write from SDRAM.

(2) Should'nt the SRAM output (Q) be a bi-directional since this pin Q has to be used for SRAM read and also for SDRAM read?

The logidc diagram I have come up with is as below:

INTERFACE -Logic ______________________________ |IF Read_SDRAM = 1 then | `````````````````` |- Initiate SDRAM Read Command |------>|SDRAM Controller| |- Addr = SDRAM_Address; | `````````````````` | | | |IF Write_SDRAM = 1 then | | |- We_n = Write_SDRAM; | | |- Addr = SDRAM_Address; | | ------------------------------ v A ******>| | | ____________ B**********>| | Addr(11-bits)--->| | C*************>| other I/Ps | | | | | ... | | V V V ... | | _____ ... | Micron | Data---->| | ------>| SDRAM | Wad ---->| |_________ Q | (168-pin) | Rad ---->|SRAM | | | | ---->|_____| | | | ^ ^ ^ | | | | | | |_______Dq (16-bits)__ | | | | | | | clk____| | | ____________ WE ________| | RE____________|

Steps to the above logic-diagram:

(1) I have allocated 3 new pins to the SRAM above namely A,B,C which are designated as:

A --> Read_SDRAM (1-bit) B --> Write_SDRAM (1-bit) C --> SDRAM_Address (11-bits)

(2) The Interface-Logic shown above programs the SDRAM Controller as to whether the SRAM wants to Read (or) Write the SDRAM. ie. the SDRAM Controller is asked to fire the appropriate Command to the SDRAM (Read, Write, Aotorefresh etc..)

(3) The SDRAM Controller then takes over by firing executing the Command requested by SRAM.

(4) Say, if the SRAM requested a Read from SDRAM, then the data read (16-bits) is sent back to the pin-Q of SRAM.

Note: that the pin-Q is also used for outputting the 16-bit data for Reading the SRAM itself!

So folks , please let me know if the above logic and its description makes sense...

Thanx, Eagerly waiting... Vick

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Hi Vick,

please find my remarks in your text below ...

Normally the SRAM should not drive the data bus if it is not selected...

Nice drawing, however is your SRAM and your SDRAM connected directly to each other, or is this done through an interface logic inside a CPLD/FPGA ??

Sorry I do not reallyy understand what you want to do. Is the SRAM kind of a memory that stores read/write request operations from/to the SDRAM ?


Reply to
Markus Meng

I find your query to be quite confusing. According to the diagram, read/write signals to the SDRAM controller are coming from the interface logic, which appears not to be receiving signals from the SRAM, but from the off-page source of A, B, and C.

Dwayne Surdu-Miller

------------------------------------------------ Vick wrote:

Reply to
Dwayne Surdu-Miller

Hello Markus,

Thanx for the reply. Ok. Here is what I want to do (Objective):

Objective:- My SRAM should be able to Read (or) Write the specified # of bytes of data from/to the SDRAM. For eg: Say I want to read 10-byes of data from the SDRAM, then my SRAM should be able to instruct the SDRAM Controller to read that many bytes from the SDRAM at the specified address. And vice-versa for writing the data to the SDRAM. Now this reminds of defining another signal- D

D --> # of bytes to be Read/Written from/to SDRAM

To answer your questions, Markus:-

- Well! I think there definitely needs to be an interface between the SRAM and the SDRAM for carrying out the transactions. So thats why I have defined the interface logic as shown in the diagram. If you are referring to the Dq (16-bits bus) directly connected to the Q (16-bits bus) then I think there also needs to be some sort of interface logic inorder to meet the timing parameters.

- I have specified this above in the Objective. Yes, this SRAM kind of memory will get the Read/Write requests, # of bytes and then process them thru the SDRAM controller as it consists Read/Write and other COmmands defined for SDRAM.

So, if the Verilog-model of any standard SRAM is say:- `````````````````````````````````````` SRAM (Data, Q, clk, WE, RE,Wad,Rad); | ``````````````````````````````````````

For my application this gets modified to as below:- `````````````````````````````````````````````````` SRAM (Data, Q, clk, WE, RE,Wad,Rad, A, B, C, D); | ``````````````````````````````````````````````````

So, the interface-logic I have shown in the diagram will go inside the SRAM block itself.

Hope I was clear this time, And am I approaching this problem with rite way,

Thanx, Waiting,


Reply to

Hello Dwayne,

Sorry, there is small correction in the diagram. Please, imagine the interface-logic to be within the SRAM block itself. So, now the SDRAM Controller receives the signals from the SRAM in order to do the read/write, from/to the SDRAM.

Also, may i request you to kindly read my follow up posting to Markus.

Thanx, Waiting for all your valuable suggestions/comments,


Reply to

I see I am not the only one who is confused by your description of the problem. I think you want to do a DMA like transfer between the SDRAM and the SRAM. But I assume this data also needs to go to or come from another source, no? Or is your SRAM dual ported so that the SDRAM is a backup for the SRAM; or better put, you are using the SRAM as a cache for the SDRAM?

In any event, I don't see how this is a very complex problem. Your description seems to be getting in your way of finding a good solution. First, I assume that all of this is running on the same clock. This is important. If they are on different clocks, then you will need to construct an appropriate interface. When you speak of the SRAM, I assume you mean a separate SRAM controller that in turn is being controlled by some other circuit. I will leave the nature of the SRAM controller to you since you have not given us any info on what this controller must do.

I would do this by constructing an SDRAM controller, like you have done, that will respond to commands. I think you have a good handle on that with the signals A, B, C, D. But you will also need a signal from the SDRAM controller back to the "SRAM" telling it that valid data is available in a given clock cycle.

To do block bursts, you can set up the SDRAM to burst as much as 256 words (or maybe more depending on the part). I believe that you can also overlap the next burst setup with the current burst data read. So you can move data continuously until the block is done. But you either need a handshake to flag when data is available, or you need to track the latency and the block size in both controllers.

BTW, you need to change your block diagram so that the signals, A, B, C, D go to the SDRAM controller which in turn drives the SDRAM signals. You may also want to show exactly how the SRAM is being read/written from the outside. This will help you design the SRAM controller.

Vick wrote:

Rick "rickman" Collins
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