Access to SDRAM on Altera Cyclone dev kit - compactflash controller

Hello,

(I'm a beginner in vhdl programmation, so excuse me if my questions seem trivial.)

I have to create a VHDL design witch runs on altera's cyclone FPGA. To do that, I use your microtronix dev board, but not the SOPC builder components. The goal of the design is to create a data storage box, a kind of hard disk where the disk is replaced by some SDRAM and a Compact Flash Card.

Does somebody know where I could find doc about this topic ? I mean, doc about making a controller for a Compact Flash Card (it should have be done yet), managing read/write between flash card/sdram/controller of the datastorage in an efficient way, etc.

I also want to be able to read/write in SDRAM and for that, I use the Altera's SDRAM controller found here :

I create a state machine to interface the SDRAM's controller and the others part of the design. This state machine manages sdram initialisation, and read/write queries. All simulations work fine, but when I load my code on the board, it does not work. I thought it was a problem with the use of onboard clocks, but it seems that there is something else : an other design which only made two write statement and then alternatively read each one works fine. I really don't know what might be the source of the problem, so what are the things I have to check ? Are there frequently done mistakes in using this SDRAM controller ? (I join my broken code and the working one)

I also want to split my big state machine in several parts which are semantically consistant : one for the init, an other for reading queries, etc. And I don't know how to handle this problem. What is 'the right way' to do this in vhdl ?

Many thanks

-------------------------------------------------------------------------------- Working design

-------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL;

ENTITY sdramInit IS GENERIC ( NOP_TIME : integer := 2; CONSTANT C_NOP : std_logic_vector (2 DOWNTO 0) := "000"; CONSTANT C_PRECHARGE : std_logic_vector (2 DOWNTO 0) := "100"; CONSTANT C_REFRESH : std_logic_vector (2 DOWNTO 0) := "011"; CONSTANT C_LOAD_MODE : std_logic_vector (2 DOWNTO 0) := "101"; CONSTANT C_LOAD_REG1 : std_logic_vector (2 DOWNTO 0) := "110"; CONSTANT C_LOAD_REG2 : std_logic_vector (2 DOWNTO 0) := "111" ); PORT ( clk : IN std_logic; data_to_mp : IN std_logic_vector (31 DOWNTO 0); rst_1 : IN std_logic; ack_to_mp : IN std_logic; data_to_sd : OUT std_logic_vector (31 DOWNTO 0); cmd_to_sd : OUT std_logic_vector (2 DOWNTO 0); adresse_to_sd : OUT std_logic_vector (22 DOWNTO 0); dm_to_sd : OUT std_logic_vector (3 DOWNTO 0); data_to_7seg : OUT std_logic_vector (6 DOWNTO 0); led1 : OUT std_logic; led2 : OUT std_logic);

END sdramInit;

ARCHITECTURE archi OF sdramInit IS TYPE TYPE_STATE IS (reset, nop, precharge, prechargeNop, loadmode, loadmodeNop, load_reg2, load_reg2Nop, load_reg1, load_reg1Nop, refresh1, refresh2, ecriture, ecriture2, lecture, lecture2, fin, wait1, wait2, wait0, fetch1, fetch2, nopn, nopn1, nopn2, nopn3); SIGNAL etat : TYPE_STATE; SIGNAL counter : integer RANGE 0 TO 255; signal nccounter : integer range 0 to 100000000;

BEGIN -- archi

PROCESS (clk, rst_1) BEGIN -- PROCESS IF rst_1 = '0' THEN -- asynchronous reset (active low) etat o_cont_commande