Hi! I am a bit new to FPGAs, so far I have only worked with CPLDs ( Xilinx9500 family ). Now I would like to use a Spartan 2E ( with WebPack 5.2 and VHDL ) to make a SDRAM controller.
I have searched this archive but I haven't found any topic related to my question. Here's the deal. When data needs to be transfered to the SDRAM the controller sends out data prior to generating the rising edge of the SDRAM's clock. So the way I see it, the fpga must generate two clocks, one for the controller and one for the SDRAM. The SDRAM clock must be by 90° out of phase of the controller clock ( the SDRAM clock must be delayed for 1/4 of the cycle of the controller clock ), in order for data to appear on DQ lines before the rising edge of SDRAM's clk. I am right so far, or am I way off? And If I am right, how do you generate the SDRAM clock ( do you use a DLL to phase-shift the input clock ? ).
Best regards George Mercury