SDRAM Controller

:Hi! :I am a bit new to FPGAs, so far I have only worked with CPLDs ( Xilinx :9500 family ). Now I would like to use a Spartan 2E ( with WebPack 5.2 :and VHDL ) to make a SDRAM controller. : :I have searched this archive but I haven't found any topic related to :my question. Here's the deal. When data needs to be transfered to the :SDRAM the controller sends out data prior to generating the rising :edge of the SDRAM's clock. So the way I see it, the fpga must generate :two clocks, one for the controller and one for the SDRAM. The SDRAM :clock must be by 90° out of phase of the controller clock ( the SDRAM :clock must be delayed for 1/4 of the cycle of the controller clock ), :in order for data to appear on DQ lines before the rising edge of :SDRAM's clk. I am right so far, or am I way off? And If I am right, :how do you generate the SDRAM clock ( do you use a DLL to phase-shift :the input clock ? ). : :Best regards :George Mercury

You run the state machine of you controller on negedge of clk and SDRAMs sample data of posedge of clock.

Sumit

Xilinx have an appnote on this. And Altera also. As for me, assuming you're talking about single data-rate:

I just ran my state machine off the same clock as the SDRAMs. If you drive the data on the rising edge, it won't appear on the outputs until some time later (about 6/7 ns IIRC for my chip), so the SDRAM will then latch it in on the *next* clock cycle.

No need to faff about generating mutplile clock domains, using negative edges or any of the other nasties. Just make sure the latency in whatever is provding the data is right.

Micron provided good VHDL models to get the simulation right - much easier than wiring up a logic analyser!

If you're doing DDR, ignore me :-)

HTH, Martin

Thanks, I will consider using both propositions! One more thing, what exactly is a state-machine? I have read this expression about a milion times in datasheets and application notes, but I stil don't know what it is.

George

Assumption: Single-data-rate SDRAM.

You're making the whole thing WAAAAY too complicated.

Your SDRAM controller should obviously be a synchronous state machine. Clock the SDRAM and the controller with the same clock -- it's common to use special clock-buffer chips to do this.

You have a synchronous controller, and you should register the data outputs, too: this way, the SDRAM command and data lines all have the same clock to out.

Say you're running your SDRAM and controller at 100 MHz (to keep the math simple). Say your FPGA (or whatever) has clock-to-out on the pads spec'd at 5 ns. Say the SDRAM has 2 ns setup and 1 ns hold times. Say you've laid out your board such that the flight time of the traces between the controller and the SDRAM is 1 ns.

This all means that command and data asserted on clock edge 1 will be stable by edge 1 + 5 ns. Therefore, that command and data are valid on the SDRAM pins on clock edge 1 + 6 ns. They meet SDRAM setup with a 2 ns margin, and will be registered in the SDRAM on clock edge 2.

In other words, it's Synchronous Design 101, and nothing special is required in order for you to meet the SDRAM's timing specs.

-a

A state machine is like a little hardwired program inside of your design.

It's called a state machine because it works on a so-called state register and a number of inputs to generate outputs, and a new value of the state register.

This state register can be implemented in umpteen ways, and how the state machine decides to jump from one state to the next can be implemented in even more ways. I'd say just look up "Moore Mealy FSM" on Google to get the hang of the idea.

Best regards,

Hello George,

I have a presentation that discusses finite state machines -- with a simple example in Verilog, at:

If you are looking for a ready-made SDRAM controller, you can find one on the Xilinx website, as XAPP134. I've used it in a project and it works properly.

Good luck, Eric