Replaceme EPROM by CPLD/FPGA

We have a product that includes a small parallel OTP memory. These devices
get very hard to get and no easy alternative is available that fits in the
very small available space. A PLCC32 EPROM will not fit unfortunately.
Since the memory array is small (256x4 bits), I was thinking this could
easily fit into a CPLD or FPGA. But how to program this?
The memory is used for calibration data. So in production, the device is
characterized, data block is calculated and programmed.
Usually you use the vendor tools to generate a bitstream from an HDL
design. But are there options to generate these bitstreams during the
production cycle, in only a few seconds? Something like HDL + DATA =
BITSTREAM. And then burn the resulting bitsream in the device.
A device like the Lattice ispMACH 4000 seems a possible candidate.
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Stef
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You could program it as a constant array. Then let the logic generate as a ppropriate. In a device like the ispMACH 4000 which has no memory, this mi ght not fit well and would require the full tool set to be used.
If you pick a device that has internal memory, you can use a part that can be placed and routed once and the contents of the memory loaded in one of t he final steps using a lot less of the tools.
That said, I have not done this myself. I have only seen it described by o thers. For a data point, our production testing programs an FPGA and it ta kes around 20 seconds for the smallish device we use. Any compilation port ion would change that to minutes, but maybe not too many for such a simple HDL file. I don't know how long it would take to load the memory. That mi ght even be doable as a separate step after the programming.
The most affordable devices I am familiar with are the iCE40 line. There a re a number of flavors so you could shop around to find the cheapest. Like many FPGAs they come in an array of packages which may or may not suit you r design. A chip scale package with 0.25 spaced balls might not suit your assembly process.
Another alternative, if the memory speed can be slow, would be to use a ser ial PROM device as your in circuit programmable memory and use an ispMACH 4 000 to turn it into a parallel device. If your calibration data is read se quentially this becomes very simple indeed and can be pretty fast once star ted.
Just kicking around some ideas.
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gnuarm.deletethisbit
Intel Quartus has an 'Update Memory Initialization File' step where you can change the memory contents of an existing project without recompiling. I don't know how much project scaffolding you'd need (you still need to run the Assembler step to generate bitfiles afterwards, so I don't think you can edit an existing bitfile). It's not super quick (maybe ten seconds for a Cyclone V) but better than a recompile.
I think some of the Lattice parts have a user flash memory but I haven't used those:
formatting link

I suppose another option is a small SPI/I2C flash chip and a CPLD that reads the contents in at powerup time. Or a NOR flash that you can program externally (but programming header with 8 address, 4 data, 3 control wires - might be too big) or another chip to drive them (I2C I/O expander for instance and a 3/4 pin header)
Does your old design have voltage requirements like 5V capability?
Theo
Reply to
Theo
Thanks for the input. Data is read sequentially, so approaches like that are doable. Access is rather slow, so if we go that route, MCU solutions (with internal EEPROM) may be possible too.
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Stef
The supply is 5V, but the interface on the reading device is 3V3 with 5V tolerant IO. So adding 3V3 regulation for the memory power should work.
Another limitation is that that the preferred programming interface is through the available connections: Address (8), data (4), control (1 + 1 tied to GND, and VCC rising to VPP). And there are 2 free pins that could be used as well.
This is a reason why parallel EEPROM (FLASH) is not an option. Those devices all require access to all address and data to enter the programming sequence. (or do you know a flash that does not require this?) Or use a CPLD to generate those sequences? (based on the states of the free pins?)
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Stef
ices
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as appropriate. In a device like the ispMACH 4000 which has no memory, thi s might not fit well and would require the full tool set to be used.
can be placed and routed once and the contents of the memory loaded in one of the final steps using a lot less of the tools.
by others. For a data point, our production testing programs an FPGA and i t takes around 20 seconds for the smallish device we use. Any compilation portion would change that to minutes, but maybe not too many for such a sim ple HDL file. I don't know how long it would take to load the memory. Tha t might even be doable as a separate step after the programming.
re are a number of flavors so you could shop around to find the cheapest. Like many FPGAs they come in an array of packages which may or may not suit your design. A chip scale package with 0.25 spaced balls might not suit y our assembly process.
serial PROM device as your in circuit programmable memory and use an ispMA CH 4000 to turn it into a parallel device. If your calibration data is rea d sequentially this becomes very simple indeed and can be pretty fast once started.
I had forgotten that the Lattice XO2 and XO3 devices have User Flash Memory (UFM) for just this sort of application (configuration data). The XO2-640 part (smallest with UFM) in a 48 pin QFN is just $3.12 qty 100. The XO3 c an be even lower cost, but only available in BGA style packaging. I found a couple of app notes on using it, one specifically for making it into a pa rallel interface RAM.
Reference Design RD1126
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gnuarm.deletethisbit
The HDL for this would be pretty short, maybe just an array declaration with the calibration data and then a single assignment to the output from the array based on the address input. So very easy to generate with a little software.
Most vendor tools have automation possibilities so the tool flow can be done with a single command. Might take longer than a few seconds though. On the other hand, if there's a limited number of bitstreams then it could be possible to generate and store all of them beforehand.
Another way could be to use the user flash memory which is included in Intel's MaxII and MaxV CPLDs. The size is 8192 bits so big enough. You'd program the CPLD with the same design and only the UFM part of the flash would need to be programmed in production.
Reply to
Anssi Saari
CAT34C02? 2Kb I2C EEPROM, small, cheap, commodity, can be locked by software, OK at 3.3V and 5V. Not as amusing as a CPLD.
Reply to
Tim
Nice reference, thanks.
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Stef
In theory there are 1024 bits, but not all will be used/changed. But even then, the number of posibilities is rather high. A few seconds is a wide range, but not into the minutes. ;-) We will see...
Ah, similar to Ricks' approach, but then with intel. Thanks.
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Stef
This is a serial interface EEPROM, plenty of those around. The required parallel interface is harder to find unfortunately.
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Stef
Den 2019-03-28 kl. 15:24, skrev Stef:
What is reading from the EPROM? What is the bus speed of the access?
I would not be surprised, if you could not implement this with a microcontroller running at a decent clock frequency.
A small Cortex-M0 chip like the ATSAMD10xxxx in a 20 - 32 pin package should be small
The program will look like this: while (1) { port = memory[pins & 0xff]; oe = (pins & 0x100) ? ON : OFF; }
AP
Reply to
A.P.Richelieu
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I find it interesting that people often feel MCUs are simpler than programm able logic. What your program in particular lacks is the important part, a llowing the contents of "memory[]" to be set at manufacturing time. I don' t see the use of an MCU to be at all simple. In addition to the above, the re is setup code that either needs to be written from scratch by reading th e MCU data sheet (starting clocks, initialize I/O banks, brown out detector s, etc., etc...) or by starting with the standard startup code and paring o ut what is not needed or appropriate.
To me, this is inordinately complex compared to the relatively trivial exer cise of creating an HDL ROM which is about as complex as the code above and setting the details of the chosen I/O pins to be used. The only remaining issue is to use the vendor tool to initialize this ROM in the compiled cod e or even in the same way it is done now which I think is done by the board itself.
Not only is the PLD method simpler, it provides a lot more flexibility.
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Reply to
gnuarm.deletethisbit
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mmable logic. What your program in particular lacks is the important part, allowing the contents of "memory[]" to be set at manufacturing time. I do n't see the use of an MCU to be at all simple. In addition to the above, t here is setup code that either needs to be written from scratch by reading the MCU data sheet (starting clocks, initialize I/O banks, brown out detect ors, etc., etc...) or by starting with the standard startup code and paring out what is not needed or appropriate.
ercise of creating an HDL ROM which is about as complex as the code above a nd setting the details of the chosen I/O pins to be used. The only remaini ng issue is to use the vendor tool to initialize this ROM in the compiled c ode or even in the same way it is done now which I think is done by the boa rd itself.

if the only thing in your toolbox it hammers, nailing things together alway s seem like the obvious choice
at slow speed an mcu could be just as viable, and customizing the array cou ld be as simple as patching the bin or hex file programmed into the part
Reply to
lasselangwadtchristensen
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rammable logic. What your program in particular lacks is the important par t, allowing the contents of "memory[]" to be set at manufacturing time. I don't see the use of an MCU to be at all simple. In addition to the above, there is setup code that either needs to be written from scratch by readin g the MCU data sheet (starting clocks, initialize I/O banks, brown out dete ctors, etc., etc...) or by starting with the standard startup code and pari ng out what is not needed or appropriate.
exercise of creating an HDL ROM which is about as complex as the code above and setting the details of the chosen I/O pins to be used. The only remai ning issue is to use the vendor tool to initialize this ROM in the compiled code or even in the same way it is done now which I think is done by the b oard itself.
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But you didn't address the additional setup required to write the code for the MCU. The ones I've used have a *lot* of features that need to be set u p for the MCU to even run. MCU code is always a lot more complex to design with than HDL in my experience.
"Patching" a hex file is not the way I want to manage configuration data. The PLD tools have already dealt with this issue.
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gnuarm.deletethisbit
fredag den 29. marts 2019 kl. 00.03.22 UTC+1 skrev snipped-for-privacy@gmail.com:
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ogrammable logic. What your program in particular lacks is the important p art, allowing the contents of "memory[]" to be set at manufacturing time. I don't see the use of an MCU to be at all simple. In addition to the abov e, there is setup code that either needs to be written from scratch by read ing the MCU data sheet (starting clocks, initialize I/O banks, brown out de tectors, etc., etc...) or by starting with the standard startup code and pa ring out what is not needed or appropriate.
l exercise of creating an HDL ROM which is about as complex as the code abo ve and setting the details of the chosen I/O pins to be used. The only rem aining issue is to use the vendor tool to initialize this ROM in the compil ed code or even in the same way it is done now which I think is done by the board itself.
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so you have only used big MCUs with piles of peripherals and advanced featu res, small 8bitters are usually nothing like that
The PLD tools have already dealt with this issue.
doing exactly the same thing, replacing the data
Reply to
lasselangwadtchristensen
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programmable logic. What your program in particular lacks is the important part, allowing the contents of "memory[]" to be set at manufacturing time. I don't see the use of an MCU to be at all simple. In addition to the ab ove, there is setup code that either needs to be written from scratch by re ading the MCU data sheet (starting clocks, initialize I/O banks, brown out detectors, etc., etc...) or by starting with the standard startup code and paring out what is not needed or appropriate.
ial exercise of creating an HDL ROM which is about as complex as the code a bove and setting the details of the chosen I/O pins to be used. The only r emaining issue is to use the vendor tool to initialize this ROM in the comp iled code or even in the same way it is done now which I think is done by t he board itself.
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for the MCU. The ones I've used have a *lot* of features that need to be s et up for the MCU to even run. MCU code is always a lot more complex to de sign with than HDL in my experience.
tures, small 8bitters are usually nothing like that
a. The PLD tools have already dealt with this issue.
So there is a tool for patching the hex data? You don't need any startup c ode on your small 8 bitter?
I think you are being a bit disingenuous about the patching issue. The MCU tools I've worked with would require quite a bit of work to replace data i n binary code.
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gnuarm.deletethisbit
No, 'the board' is connector + PROM on a very small piece of FR4, programmed in a universal programmer. There is already software generating the data to be programmed.
And yes, an MCU is a possibility as well. And as I am much more comfortable in programming MCU's, I think I can handle the software involved for MCU and data generation. ;-)
But I see a CPLD (or FPGA) as a solution as well and was wondering how I would approach such a solution. That why I asked in an FPGA group.
Startup usually comes with the tools. Just start a new project for the specific controller and everything is set up to defaults and you just have to write your main() and set the peripherals (which would only be GPIO in this case). You may want to check the oscillator setup in the startup. And if you use a higer level tool (like STM32CubeMX for ST controllers), you can let it generate most of the peripheral init code.
I think this could be done with the linker. Just add a section with the calibration data at a fixed address. Or maybe even better (does not require linker during production), there are plenty of hex file tools and I would be suprised if there is not one that allow adding a bit of data. And if there's nothing, writing something like that in C (or Python or Perl or ...) is not too complex (and I think I even have hex file code in C from old projects somewhere). But all this is not so relevant for an FPGA group, I suppose.
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Stef
It appears there's a core for making a MAX CPLD look like an I2C EEPROM:
formatting link
I haven't used these cores, but assume a mux could be interposed between this core and the flash, to allow access to the flash in a parallel manner in addition to via I2C.
The OP could put a MAX part on their module, and use the spare two pins on their module to provide an I2C programming interface. The bitfile is programmed at manufacture time (some JTAG pads on the module or pre-program the chips) and the memory can then be field-programmed via the I2C pins on the connector.
Theo
Reply to
Theo
I don't know about others, but I prefer easy to work with packaging. I find most FPGAs come in hard (for me) to use chip scale or BGA packages (very large pin counts). The Lattice parts at least are available in QFN packages.
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