We have a product that includes a small parallel OTP memory. These devices get very hard to get and no easy alternative is available that fits in the very small available space. A PLCC32 EPROM will not fit unfortunately. Since the memory array is small (256x4 bits), I was thinking this could easily fit into a CPLD or FPGA. But how to program this?
The memory is used for calibration data. So in production, the device is characterized, data block is calculated and programmed.
Usually you use the vendor tools to generate a bitstream from an HDL design. But are there options to generate these bitstreams during the production cycle, in only a few seconds? Something like HDL + DATA = BITSTREAM. And then burn the resulting bitsream in the device.
A device like the Lattice ispMACH 4000 seems a possible candidate.