EC/ECP Map Problem

Feb 25, 2005 1 Replies
A

Hi FPGA people,



I am trying to map my VHDL design on a Lattice-EC FPGA. (LFEC20E-5F672CES)



The following error warning occurs:


********************************* Map checkpoint failed. Design's logic delay (97 percent of total delay) exceeds the 60 percent limit set in the map checkpoint options
********************************* Process Stopped.

Done: failed with exit code: 0001.


Unfortunately there is no direct "double click" HELP for this error message and I could not find any hint in the HELP menu.



Has someone of you any idea what this message could mean ?


Thank you in advance.



Rgds Andrés


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G

(LFEC20E-5F672CES)

This would be a lot clearer if it named a particular path. This is like the old Xilinx post-translate timing, where the place and route will not continue if it already knows it won't meet timing. In the Lattice case it seems that there is also a threshold of 60% of your constraint (in Xilinx it was 100%). i.e. if you gave a path 10ns and with logic only (no routing) you've already used more than 6ns it gives the error. The "map checkpoint options" sounds like there is a way to control this percentage. All of this is speculation on my part since I don't have the Lattice tools yet, but I know that there tools were developed by some ex-Xilinx types...

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