I made use of two 1K*10B single port RAMs generated with coregen which is modified to contain my test vector, and P&R with that. However, I have one thousand test vector files in plain text to send to the FPGA one at a time.
I am wondering about whether I can write a perl script to manipulate the bitstream and generate an *incremental* bitstream so that I can avoid running ISE for one thousand times? Where can I find such information?
Thanks.
Check the "data2mem" program installed with ise.
HTH, Jim snipped-for-privacy@yahoo.com (remove capital letters)
one
Thank you Jim.
I was aware that data2mem takes in a FULL bitstream of my compiled design, and output an updated FULL bitstream of the design. Since I am using a Virtex
6000, the time required to configure the FPGA becomes intolerable.I am able to wrtie automation scripts to employ the "small bit manipulation" trick to compare two bitstream and get a differential partial bitstream, but I am concerned whether this is the right approach.
Besides that, is it possible to automate the Impact to configure the FPGA, for example,
1 configuration per 5 minutes, since I intend to do some exhaustive test of all the 1000 input vectors.
manipulation"
of
You can run IMPACT in batch mode and control the time interval between configurations via a script.
HTH, Jim snipped-for-privacy@yahoo.com (remove capital letters)
I would do (have done) it that way : Tcl script driving your PC's RS232 (OTOMH around 30 lines of code with a GUI), then use our free UART (or any other) in your Virtex (you need one wire and an RS232 level translator, but usually the -well designed- boards have this already.
On Altera parts, we now often use the In-System Memory Contents Editor which updates Rams in real time through the JTag connector (no design, no utility to write, real handy). I don't remember if Xilinx has the equivalent of ISMCE.
B.R.
Bert
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