Picoblaze development tool

Recently I have updated my Picoblaze (tm Xilinx) development tool pBlazIDE and added some documentation. Additionally I have published some example code and demonstration files. Please feel free to check this out. Its all freeware. Check under 'Tools'.

Regards, Henk van Kampen

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Henk van Kampen
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Dear Henk,

Could you explain what we can do with your JTAG option ? Can we do on-chip PicoBlaze debugging or ROM download ?

If yes, this is very interesting.

Actually, we are working on reconfigurable high speed automat machine. We will try to use picoblaze as base. One automat will have about 10 to

100 picoblaze. The goal is to keep the speed and true multi-processing achitechture of sequencial function.

Laurent

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Reply to
Amontec Team, Laurent Gauch

Dear Laurent:

That is the idea. You can generate an SVF file by including in your source file: SVF "testjtag.svf"

It will generate an SVF file based on the specifications in the JTAG tab of the settings dialog and your source. Since this is still in its infance please let me know is this is useful or what to change/add. Since your are an probably an expert on JTAG considering your Chamelion product I welcome your advice.

Very interesting. You will, however, need a lot of blockrams. And with the JTAG option you can not use two PB's with one blockram. By the way, how do you want to let the PB's communicate? One of my own wishes for pBlazIDE is to be able to simulate several PB's in cooperation. This will need some for of inter I/O port, which needs to be simulated and therefore some how specified. I also have used more than 1 PB in a design and have them communicate but that was by some form of dual-ported RAM. So let me know what your ideas are.

Henk van Kampen

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Reply to
Henk van Kampen

Thanks a lot for your effort. I found my KCPSM source cannot pass the IDE asemble, but it had passed the KCPSM.EXE of Xilinx and generated VHDL code for synthesis. In my source, the "input sX, (sY)" instruction were reported as "?Closing". Some labels ahead instructions were reported as "?Phasing", but some were OK. Why? Besides, what's the difference between "open file" and "import file"?

"Henk van Kampen" : snipped-for-privacy@posting.google.com... : Recently I have updated my Picoblaze (tm Xilinx) development tool : pBlazIDE and added some documentation. Additionally I have published : some example code and demonstration files. Please feel free to check : this out. Its all freeware. Check under 'Tools'. : : Regards, : Henk van Kampen :

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Reply to
louis lin

Why?

pBlazIDE uses a somewhat different syntax than KCPSMBLE. You should leave out the brackets around the second register. The INPUT opcode is INP. You can find the opcodes and directives for pBLazIDE on the web at

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?Phasing errors occur because of mismatches of labels between the 1st and 2nd pass. They can occur when some instructions are accepted by the 1st pass and not by the 2nd. Probably this is because of the differences in opcodes as explained.

'open file' reads the file as is. 'import' file is meant to convert the file while reading, from KCPSMBLE to pBlazeIDE syntax.

Regards, Henk van Kampen

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Reply to
Henk van Kampen

We are interested to do something in this way. I will ask my Team about the idea to do a OCD (On-Chip Debug) solution for the PicoBlaze.

We have a relative good knowledge about JTAG on Arm processor. For the PicoBlaze, we have to add, in the PicoBlaze, a small register bank for On-chip debug solution including breakpoint fsm and to read back the PicoBlaze registry. We have naturally to think about the possibility to chain multi-PicoBlaze boundary Scan together

Do you know if Xilinx have a support or source for On-chip debug machanism on JTAG ... other way we will do that!

Then, we will use our new very low cost pockeTAG POD based USB to play the JTAG TAP to accelerate the job. And we will give you instructions for upgrade your software with our OCD solution, to be able to mark the breakpoint and to execute the on-chip debugging step.

Our new POD will be about $89.-, and can run JTAG trace at the same speed that Cable IV (for download without verify, we are a better datarate on the JTAG !) but it works over USB with the big advantage of the power from USB, on MS and Linux. JTAG target can be 1V, 1.2V, 1.8V,

2.5V and 3.3V with 5V IOs tolerant! It can be a good solution for this JOB too. A low cost On-chip debug solution for a free Picoblaze Processor!

Yes you right, and when I saw the SPARTAN-III architecture, I thinking this was not a good idea. The RAM is bigger, but too much regrouped for this JOB.

But for the first run we will do the job with 10 Picoblazes.

Before, we have to contact Xilinx if they are interested or if that too much for this small PicoBlaze.

Laurent Gauch

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Reply to
Amontec Team, Laurent Gauch

Thank you very much for your reply. After some modification, my program was able to pass the assemble and progressed the simulation. May I ask another stupid question: Where is the I/O panel? How can I invoke it during simulation?

Best regards, louis lin

"Henk van Kampen" : snipped-for-privacy@posting.google.com... : : pBlazIDE uses a somewhat different syntax than KCPSMBLE. You should : leave out the brackets around the second register. The INPUT opcode is : INP. You can find the opcodes and directives for pBLazIDE on the web : at

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: : ?Phasing errors occur because of mismatches of labels between the 1st : and 2nd pass. They can occur when some instructions are accepted by : the 1st pass and not by the 2nd. Probably this is because of the : differences in opcodes as explained. : : 'open file' reads the file as is. 'import' file is meant to convert : the file while reading, from KCPSMBLE to pBlazeIDE syntax. : : Regards, : Henk van Kampen :
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Reply to
louis lin

progressed

: snipped-for-privacy@posting.google.com...

Please have a look at the directives page at the web site. You should use DSIN, DSOUT or DSIO to simulate I/O visually.

Henk van Kampen

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Reply to
Henk van Kampen

Henk

Thanks for the notice. Is there any chance you will have a C compiler available for picoblaze?

Reply to
Pete Dudley

Not likely since the architecture of Picoblaze is not compiler friendly; it lacks a data stack which needs to be simulated or done by registers but then there are to few of them. A kind of pseudo C with control structures would be possible and can be useful, but this could be done with macro's. May be in a future release.

Henk van Kampen

Reply to
Henk van Kampen

Laurent:

Do you have a target date for the release of the USB based JTAG pod? Also any specs on what it will support?

Steve Buchholz

Reply to
Stephan Buchholz

Steve,

It will support

- all Xilinx components, FPGA CPLD EEPROM FLASH configuration over JTAG (programm + verify, with X devices on the JTAG chain)

- FPGA configuration SLAVE SERIAL MODE

- True I2C generic port for onboard I2C-EEPROM configuration and other I2C-chip configuration.

We will add more features in the future.

I will do notification on the begin of 2004 when our pockeTAG is ready to use and buy.

Laurent

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Stephan Buchholz wrote:

Reply to
Amontec Team, Laurent Gauch

Steve,

It will support

- all Xilinx components, FPGA CPLD EEPROM FLASH configuration over JTAG (programm + verify, with X devices on the JTAG chain)

- FPGA configuration SLAVE SERIAL MODE

- True I2C generic port for onboard I2C-EEPROM configuration and other I2C-chip configuration.

We will add more features in the future.

I will do notification on the begin of 2004 when our pockeTAG is ready to use and buy.

Laurent

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Stephan Buchholz wrote:

Reply to
Amontec Team, Laurent Gauch

JTAG

Not just windows based hopefully ? How about linux support as well ?

Alex

Reply to
Alex Gibson

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