rocketio decoupling

Pretty sure you only need to decouple the rocket I/Os you're using. You could email Ed McGettigan to find out the official Xilinx line, his email address is in his posts here. I believe he knows about the ML board too. Best, Syms.

We did a rewrite of this section in the user guide (page 110) to clarify this, but when I reviewed it again today it's still not clear. What it should state is 1.0 uF for every 2 MGTs that are used and these should be placed near the ferrite beads, which should be placed near the FPGA.

If you are looking for an example of how Xilinx created a board that uses the RocketIO, the ML300 is not a good choice as this was done very early and is missing some of the final design recommendations.

The ML310, ML321, ML323 and ML325 are better examples in this area

Ed

So, the 8 x 1uF capacitors aren't actually required regardless of how many MGTs are being used which seems to be the meaning in the UG ver 2.5?

If I've got a XC2VP2 and am only using 2 RIOs, do I only need 1 x 1uF then?

Thanks,

Roger.

That's right, a single 1 uF in addition to the 330 uF near the LDO.

Ed