Microcontroller decoupling, >1uF rules?

One needs of course to be careful about plane resonance as shown in figure 2 of this publication:

Ahh, I dunno about that even on an 8 bit AVR the SLEEP instruction takes a full clock cycle to execute, and the program counter has to finish updating itself into the PC = PC + 1 state before the core clock is shut down and responsibility is handed off to the wake controller/watchdog timer.

Also any microcontroller of significant complexity is going to have pipelined execution; even the AVR has 2 stage fetch/execute, and when it hits the SLEEP instruction you know with certainty a branch is going to occur later to an interrupt vector when it comes out so everything in the pipeline after it is junk and needs to be flushed.

I think there need to be some housekeeping tasks done before it can just drop into sleep and how quickly it can do them depends on if it has special ability to identify the sleep instruction earlier in the pipeline than others, but I don't think anything can start moving with respect to shutting stuff down until the PC is updated and the pipeline flushed at minimum.

That usual family of curves is mostly silly.

Except for vias. The usual capacitor VNA fixture doesn't model a PCB very well. Simulations don't either.

We usually do a ground layer and various power pours on adjacent layers, and seed that with 1 uF caps most anywhere. That always works fine with uPs and FPGAs.

I've TDR'd those structures and see no plane resonances. Sometimes a tiny hint of edge reflections. Qs are low.

Agree, the planes themselves are the best HF caps.

Lots of big FPGAs have substantial (as in 1 uF) on-die capacitance, so external bypassing is just for any slow stuff. I've tested some NXP Arms that seem to have none.

I'm doing some 10 GHz wideband precision analog stuff now, so I do use a lot of 1 uF 0306 caps right at the IC pins with big copper ground pours just outside, all on layer 1.

Many people try to simplify power distribution system design to a few simple rules of thumb like a single 0.1 uF cap for each power pin. This is not based on anything specific to your design or even the chip that is being decoupled, yet many follow such rules. As Lee Ritchey said, "No one ever got fired for using too many caps in a PDS".

Your analysis is based on various assumptions you have made. The only way to actually know what is happening is to either get the decoupling information from the chip manufacturer or to build a test board and measure it yourself.

Keep in mind that while the chip has internal currents that create fast spikes, the currents required to drive output signals can also produce significant current spikes on the power rails.

Processor designer talk about "gate delay". For fast processors typical rules would have 12-20 gate dalays per clock. which means that during clock cycle signal has time to pass for say 20 gates. For slower ones (like your 100MHz case) more likely 20-50 (allowing pass trough more gates means that number of gates can be minimized, giving slower but smaller core). Also, effective delays are largely due to parasitice capacitance. So, transistors are likely to be much faster. They switch with limited speed because they are driven by slowed-down signal, but still I would expect closer to 0.3ns.

No, for various reasons:

1) normal SLEEP does not stop clocks and keeps peripherials running. Only core is stopped. Various "deep sleep" variants are multi-clock. 2) during cycle transitions goes trough several layers of gates and signals need to propagate trough transmisson lines. So "stopping" need to propagate and it takes time. 3) Significant power (say 1/3 ot total core power) goes into clock lines. For sleep new clock transition is stopped, but at time when new transition should happen clock line is quiet (this is related to point 2). 4) There is a lot of internal parasitic decoupling.

At that frequency inductance of leads and traces is quite significant. So it matters where you want your transient. AFAICS insided chip it is really to chip designer, all you can do is to get capacitor as close to chip as possible. OTOH I would expect transiton to be slowed down by internal filtering.

Single cap per pair of power pins, otherwise inductance of traces plays role. Since transitions are much slower than you assume you may get away with single cap in purely digital circuit (but you probably will exceed 100mV limit on transients).

Well, it depends how much low frequency filtering is needed. Classic 0.1uF is enough for high frequencies. Due to inductance you want capacitor per power pins pair and it makes sense to use capacitors of the same value. OTOH 2.2uF after 2.2uS with current 100mA will drop by

100mV. So you probably want more low freqency filtering. Also, it makes sense to add electrolytic (or RC) to dump resonances.

In modern FPGAs, local equivalent gate delays are picoseconds. The big delays are wiring. SERDES blocks are fairly complex and clock at 10s of GHz.

Tantalums have nice ESRs, to keep regulators happy. Polymers are better to provide surge currents.

Our universal bypass is 1 uF 50v 0805, which we use on supply rails up to 24 volts.

I'd be surprised if "physical layer" stuff was the main bottleneck on how fast a processor can drop into deep sleep, there's usually executional house-keeping that needs to be performed like setting/resetting flags and flushing the pipeline. AFAIK even in processors with branch prediction/speculative execution all sleep instructions are somewhat the equivalent of incorrect speculation, you can't predict what's going to happen after that or what external or internal trigger will bring it back out.

On a sunny day (Wed, 20 Oct 2021 01:40:15 +0200) it happened Klaus Vestergaard Kragelund snipped-for-privacy@hotmail.com wrote in <sknl0u$1bl9$ snipped-for-privacy@gioia.aioe.org>:

I use 100 nF on my PICs 18F14K22 directly at the pins. those run at 64 MHz Never a problem As to the dip in supply caused by switching modes those PICs for example are good for: VDD Supply Voltage PIC18LF1XK22 1.8 -- 3.6 V FOSC < = 20 MHz 2.7 -- 3.6 V FOSC < = 64 MHz 85°C 2.7 -- 3.6 V FOSC < = 48 MHz 125°C

So if you run from say 3.3 V a 600 mV dip should be no problem (in theory anyways) Further down the road there is usually a bigger electrolytic capacitor, so slow variations as due to mode switches as into sleep are no problem. Other micros I know are very much the same. Load variations on the processor pins by the rest of the circuit may be several mA and probably more important and in that case your supply caps and stabilization need to be able to handle that.

The device I am looking at, just for example, is the STM32F750V8

It actually has a seperate core voltage, so transients from the core switching is isolated with an internal LDO. The LDO seems to be decoupled with 2x 2.2uF. There is an option to run the core directly (page 28 of the datasheet), at 1.2V

So it seems a instruction sleep won't be passed with the 1ns transient, but be smoothed out of the 2x2.2uF and the series regulator.

As others suggested, then the direct loading of CPU IO pins are maybe more direct impact on the PDN system

Regards

Klaus

Supply network antiresonances (i.e. parallel resonances) do exist and can cause problems. The solution is to sprinkle some alpos around among the ceramics. They look like small resistances at the typical resonance frequencies, so they damp the antiresonances very effectively.

Cheers

Phil Hobbs

Those 2.2u caps seem to be external.

I wonder if it has any on-die power bypass capacitance. You could measure one and see.

For the small embedded controllers, they don't have embedded capacitors. I have seen the insides of one, only a chip

Bruce Archambeault has done a lot of work on this

For applications below 500MHz, going from power oin directly to the plane with a via has best performance, and the capacitors can be spread out on the PCB if proper power planes are used

The bigger Xilinx chips seem to have caps integrated into the monolithic die, so they wouldn't be visible.

That's cool. Some serious real-world mythbusting.

Just scatter a lot of 1u caps around the pours!

My audio circuits typically filter Vdd with a large capacitor in parallel with a 100 nF capacitor. See C1 and C2:

VSLI uses a similar scheme. See C1, C2, C18 - C26:

Danke,

I knew a guy at Lockheed who didn't use any bypass caps on multilayer logic boards. His stuff worked too.