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Clock Domains with PLL

Hi all, my question is not really related to FPGAs (so let me know if there is a more appropriate forum), but I think it is of some relevance.

Anyway, I have a design that contains a 75 MHz clock, and a PLL that multiplies it up to 300 MHz. These two clocks will be in sync except for the jitter the PLL introduces. Also, the 75 MHz clock is FM modulated to spread its power spectrum out, but the PLL should track this. I'm wondering about the best way to synchronise signals between the two clock domains; I have two state machines that need to do a small amount of communication. I could simply place some flip flops to sync the signals, but I get the feeling that the chance of metastability will be much higher, since the two clock domains are related by the PLL. Is there any particular method that works well in this situation?

Thanks in advance,

Michael Chan.

Reply to
Michael Chan
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HI You should divide 300MHZ to 75 MHZ and try synchronise this clock domains. For devider use simple counter , it should works. WZ U¿ytkownik "Michael Chan" napisa³ w wiadomo¶ci news:newscache$xab3ai$oml$ snipped-for-privacy@lbox.itee.uq.edu.au...

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Reply to
FPGA_com

I'm not sure what you are saying. My 300 MHz clock is in fact divided by four in the PLL loop, but I'm not sure how this helps in synchronizing signals between the two clock domains. One of my concerns is if the jitter between my two clocks minus the propergation delay of a flip flop is greater than the setup time of a flip flop. In this case, if I have two flip flops in series where each flip flop is triggered by a seperate clock, I will lose a bit of data, and incorrect data will be latched (hopefully that is clear).

In any case, this seems a common enough problem that there might be some tried methods for dealing with it; any ideas?

Thanks,

Michael.

Reply to
Michael Chan

I suppose your two frequencies (75 and 300 MHz) are rising-edge aligned. If you run your 300-MHz logic off the falling clock edge, then you have half a period of 300 MHz = 1.5 ns of protection. But you have also lost that much time for the interface, so this works only if the clock-straddling interface is very fast.

The previous posting suggested you start with 300 MHz, and derive 75 MHz from it. My suggestion would then be to run everything off the 300 MHz clock, and use CE to achieve 75 MHz operation. Your modulation makesthe whole thing more complex... Peter Alfke

Reply to
Peter Alfke

I don't know about your design, but my favorite is to invert one, which keeps their rising edge about a half cycle of the fast clock apart. Then latch them at the boundary, so you have the full clock cycle available.

More than metastability is the possibility that some signals will be latched before and some after a clock edge. That is the reason to use gray code when FIFO pointers cross a clock domain.

-- glen

Reply to
glen herrmannsfeldt

I guess this is the obvious choice; I'll just have to be careful.

My original design had everything running off of 300 MHz, but the PLL is disabled in slumber mode, so this clock is not always available(something which I found out about after I had finished *sigh* ).

Michael.

Reply to
Michael Chan

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