Hi!
I've been having a really weird problem with a Xilinx Virtex-E XCV1000E development board from AVNET. I've got a VHDL design that I've been working on since october last year. When I upload the compiled design into the FPGA, everything works fine except after a couple of seconds (10s or so), the board resets itself and the FPGA is reprogrammed with the onboard design.
(There is a sample design in an onboard ROM chip. I download my design via the JTAG interface.)
When I take an old design (Tuesdays' in fact), everything runs fine and stable. The only change is that I make two instances of a module instead of one. The module is a self-written serial multiplier with RAM and ROM. The only difference between the two instances is a different ROM configuration (ROM data). The input lines (20-30 lines) are identical and the output lines (three of them) are treated very similar.
I have already consulted my University colleagues, but so far without results. I already checked temperature, the clock/reset nets and I/O pin assignment. Everything looks fine to me, but I'm certainly not an FPGA wizard...
Any ideas? Any recommended course of action?
Thanks for your help!
Cheers,
-- Ulf