Hi all,
I need to build a 120 cells FIFO (cell = 24 bits) and I wondered what is the best way of doing it.. My FIFO should work like a shift register, i.e. - each write strobe it should load a new value to the 1'st cell and discard the 120'th value.
I'm using the Xilinx Spartan 2e FPGA. The write strobe frequency is 1Hz - so frequency is not an issue.
p.s. - I'm fimiliar with the CORE GENERATOR FIFO but I dont know if it is the best solution.
Thanks in advance, Moti.
Moti, This is more like a shift register than a classic FIFO. You don't need the complexity of the coregen fifo for this. There are two approaches you can use: the first would be to use SRL16 elements. You'll need 8 chained together (I recommend using flip-flops after each SRL16) for each bit, or a total of 192 SRL16's. This is advantageous if you need the BRAMs or the layout is such that the BRAM concentrates the routing too much to meet timing. The other solution is to use dual ported BRAMs, using one port for read and one for write. You can use them as 256x16, and either use a single mod 120 counter with a register delay for the write address, or use a pair of counters with one initialized at -120 relative to the other.
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--Ray Andraka, P.E.
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Thanks Ray - Its always educating to read your answers. However In this kind of applications I tend to be a little lazy so I eventually found a xilinx core generator block calld a "ram based shift register" that completly suits my application so I went for the easy way..
Regards, Moti.
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