Hello there,
I am working on a FPGA project that requires to interface the FPGA with an array of serial 12bit DAC. I can not use parallel 12bit DAC simply because I don't have enough pin counts on that FPGA (360 pins are needed if use parallel DAC). So I plan to write a synchronized serial interface (clk, data, sync) to pump the data out as soon as the 12bit data is generated inside FPGA. I image that I probably need a shift register, PLL ( generate clocks for both shift register and the DACs), a bit counter to signal the end of transmit? Does anyone have the experience to do this? Please help.
Thanks
Mike