Xilinx Virtex4 / Spartan3 High Speed Designs

Hi Matthias,

In my honest opinion, even with FX series, 450 to 500 MHz. will be extremely difficult to achieve.

For 500 MHz. , I would recommend using external low jitter clock. Check DCM's jitter spec and see if that is tolerable to you, else stick with epson clk driver. Also differential clock driver is that you are looking at those frequencies.

As far as advertised speeds of 500 MHz. it might be achievable on their DSP family of devices especially their hard DSP macros.

As far as your other question, about cooling the device and increasing core voltage to run at higher clock frequencies, you might possibly damage the device. Check with Xilinx about it. Make sure you are talking to right FAE about such issues to get correct answer.

Finally I would shoot for 300 to 350 Mhz. max with FPGAs. However most of it will depend on the size of design and part selected. Larger the part, more likely you will have trouble hitting the frequencies.

Regards,

Purvesh

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As I mentioned in the seminar, 500 MHz is achievable in most blocks, but a complete 500 MHz system may be tough to put together, since it means that you must never loose even a fraction of a ns. If Matthias needs 500 MHz, I invite him to send me some specific ideas and requirements, so we can take a look at the feasibility. I tried to mail him directly, but his e-mail address is camouflaged. Peter Alfke, Xilinx Applications snipped-for-privacy@xilinx.com

Hi Peter,

Can you tell us eagerly awaiting the -12 Virtex4 devices when we can expect them to be available in ISE? I've heard that they will be in ISE

Thanks, Kevin

A few additional comments: LX, SX and FX inherently have the same speed for a given speed grade. (LX and SX are just a different mix of identical functions, "gin&tonic vs. tonic&gin", FX adds PPC, MGT and EthernetController to it.) In many cases, we are quite conservative. I know that the DSP core runs much faster than 500 MHz, and so might the BRAM. For a production design, that does you no good, the part "is" only as fast as the vendor guarantees. But if you want to tinker, you might be surprised. Keeping Vcc at the high end (but stay within spec!) helps a few %, and so does a heatsink, to keep the junction temperature below the specified max 85 degree limit. I am always interested in designs that challenge the max performance. When I joined Xilinx 17 years ago, I designed a 40 MHz counter. You cannot imagine the logic contortions required to do that in an XC3020. Now I'm thinking of (ab)using the MGTs to count up to 5 GHz, and also to do frequency synthesis up to 5 GHz. Maybe later this year...It helps to think ahead. :-) Peter Alfke, Xilinx Applications

Kevin, you heard right:

-12 speedfiles will be in ISE 7.1, available later this month (February ). Peter Alfke

Sounds good - you will make this public ? - and perhaps do two versions, one that is FPGA generic, and one (clearly faster) that is as heavily HW optimised as possible.

I'd also suggest adding Pulse Width Synthesis, to Freq measure, and Freq Synthesis (DDS?)

-jg