Major thanks to Mike Tressler, Peter Alfke, and Philip Freidin for all of the advice concerning my syncronization problems, specifically the dreaded 'data crossing clock domains' problem. I had a good feeling this might have been contributing to my difficulties, but you folks put this into words in a way I could understand WHY it was causing problems, and also offered suggestions for remedying the situation. I'm happy to report that I have completely cleared all of my issues 100% as of this morning! All of the strange behavior has now been explained, and I have a much more solid understanding of how to write these things properly in VHDL! :D
Special thanks to Philip Freidin - there was a usenet article of his I dug up out of the archives from Dec 2001 that specifically explained the clock-domain-crossing problem, and an elegantly stable solution for reliably detecting asyncronous clock edges coming from other domains. It can be found here:
Thanks again guys - this has solved an incredibly irritating problem that has been eating at me for the past two weeks!
All the best,
-- Matt