Re: Thinking out loud about metastability

Voting circuits don't work as a metastability cure. Imagine a

Back in the early 80's, UCSD professor Leonard Marino wrote a paper in which he very thoroughly analyzed a number of alleged metastability cures, one of which was the voting circuit. I can't find my copy of the paper, but it must have appeared in IEEE Transactions on Computers.

Bob Perlman Cambrian Design Works

True on both counts. But how do you do make the output stable? This is the point at which folks have tried adding hysteresis, etc. And we've all been down that road before, I think.

Bob Perlman Cambrian Design Works

Well, just because the manufacturer isn't putting the info in the data sheets, and don't test for it, I suspect that you could get a rough description that could be quite helpful. Knowing, for instance, that the strobes will always follow a CPU clock by at least

If you can just get the roughest of descriptions of the clock vs. strobes circuitry, you can improve the system performance greatly, because you don't have to have ranked FFs on every strobe.

Now, on the high speed stuff, with clock multipliers, etc. it can get quite complex, and a CPU swap to the next higher speed can throw everything off due to a change in clock multiplier. But, I gathered from the initial post that this wasn't a clock multiplied CPU.

Jon

I agree.

The odds that one synchronizer will work without error is always better than the odds that two synchronizers will work without error.

The voting circuit only works without error only if two of the three synchronizers work without error.

-- Mike Treseler

What if one FF says '1', one FF says '0' and the last is someplace inbetween?

This

there

is

tell

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

I am embarrassed. I fell into the "fix metastability trap". To quote a German proverb: "Alter schuetzt vor Torheit nicht" (Age is no protection against stupidity).

So, before anybody starts experimenting: Three or more flip-flops with majority voting are no cure for metastability, they just protract the agony. And so do all sorts of other schemes. All of them! But, as Hal wrote, just waiting helps. And you do not have to wait very long. Clocking the synchronizer result at 300 MHz into a second flip-flop gives you the "wrong" result once in a billion years. ( and we can debate what is actually right or wrong ). The uncertainty of 0 or 1 is never the issue in metastability ( either answer is as good as the other), it is the unpredictable timing that is the bummer. Since that range of unpredictability (is that a word?) is statistically less than 2 ns for any reasonable probability, we can ignore metastability in all but the very fastest applications.

But we cannot fix it, not with voting, nor with hysteresis, nor with any other contraptions.

My thanks to Bob Perlman for kicking me in the shins. It's good to have friends. :-) Peter Alfke

I proposed some time ago that injecting a high frequency signal into the FF feedback path would limit metastabilty maximum duration.

You drop a pin onto a table now and then it will land perfectly balanced on its point, how long it stays upright depends on how well it was balanced.

Vibrate the table and it will stay upright for less time.

I don't think so.

This is another example of a "fix". They don't work. The only question is can you see why they don't work?

In this case, the vibrations will kick some pins that have started to fall back to the ballancing point.

Except that you don't know that this won't change if they tweek the chip design. It could very easily be 1 to 5 ns delay now and then change to

Actually, yes the MCU runs at 8x or 4x the input clock. But the output is at the MCU rate and I will be clocking the FPGA with the 8x MCU output clock.

Question: When a D-type flip-flop is in meta-stability, is it's output (Q pin) voltage equal to the input (D pin) voltage?

If it's not the same voltage, then a cascaded flip-flop, clocked just after the first one, would not be in meta-stability! Isn't it?

Luiz Carlos

The output level of a flip-flop during its metastable time is irrelevant. If it were in the middle ( which it isn't) we could easily fix this with a zener diode. The problem is timing. The Q output can - and will - change to the opposite state at a totally unpredictable time. That's the problem: unpredictable timing, not unknown levels.

Cascading flip-flops is the standard remedy, but it introduces latency.

Remember: Metastability causes an extra 3 ns of unpredictable delay >

Very well put. I think it is so well said that it sould be added to the FPGA FAQ. There is a comp.arch.fpga FAQ, right?

Thankyou Philip. But as I said, I don't believe "There is no cure for metastability", or any other problem. It's just a question of time.

Luiz Carlos.

Luiz, you need to read up on metastability. There are things even in physics that have no solution. Perpetual motion is one. If you want to get philosophical about metastability, read Heisenberg's Uncertainty papers.

Phil Freid>

Yep, you are right, it is just a matter of time. In this case it is infinite.

When you do your designs do you

A) Do nothing special for async signals entering a synchronous domain, because some day someone will solve this problem.

or

B) Use multistage synchronizers to move signals from one clock domain to another, because some day someone will solve this problem, but it hasn't happened yet.

or

C) Not sure, because I haven't ever seen this problem.

Philip

You can make the capture window small, but there is always a finite chance that you will capture the metastable point.

Basic calculus: IF a curve has two local minima (the stable points), there must be one local maximum (the metastable point) between the two. If you happen to capture the input data when it is at the metastable point, metastability/unstable equilibria happens.