Re: EDIF input to Xilinx ISE

The & is used to allow identifiers to begin with an _ or a number. Make sure your files are purely structural. EDIF2NGD only supports EDIF 2.0.0. What's worse: the error messages can be off by thousands of lines either direction. What's worse than that: the memory efficiency of the tool is terrible. As far as a "conversion tool" is concerned, get the parser from

formatting link

for the 2.0.0 files. Run your code in and out of there. The pretty printed version from that should work better. I have plenty of EDIF files that will work with the EDIF2NGD tool Xilinx ships. Here's an example:

(edif Test (edifVersion 2 0 0) (edifLevel 0)(keywordMap (keywordLevel 0))(status(written (timeStamp 2003 5 20 15 25 35)(author "SBS")(program "SBS" (version "Whoopee")))) (library Test (edifLevel 0) (technology (numberDefinition )) (cell GND (cellType GENERIC) (view net (viewType NETLIST) (interface (port G (direction OUTPUT)) (property LEVEL (string "XILINX"))(property LIBVER (string "2.0.0")) ) ) )

(cell VCC (cellType GENERIC) (view net (viewType NETLIST) (interface (port P (direction OUTPUT)) (property LEVEL (string "XILINX"))(property LIBVER (string "2.0.0")) ) ) )

(cell OR2 (cellType GENERIC) (view net (viewType NETLIST) (interface (port I0 (direction INPUT)) (port I1 (direction INPUT)) (port O (direction OUTPUT)) (property LEVEL (string "XILINX"))(property LIBVER (string "2.0.0")) ) ) ) (cell someOr (cellType GENERIC) (view net (viewType NETLIST) (interface (port In1 (direction INPUT)) (port In2 (direction INPUT)) (port Out1 (direction OUTPUT)) ) (contents (instance I234OR2 (viewRef net (cellRef OR2))) (net N1727(joined(portref O(instanceRef I234OR2) ) (portRef Out1))) (net N1728(joined(portref In1 ) (portRef I0(instanceRef I234OR2)))) (net N1729(joined(portref In2 ) (portRef I1(instanceRef I234OR2)))) ) ) ) ) (design Test (cellRef someOr (libraryRef Test))(property PART(string "xc2v6000ff1152-4") (owner "Xilinx"))))

Hello,
>
> Has anyone had any success with creating schematic pages with other
> tools and then getting ise 4.1.03i to accept it (preferably as an edif
> file)?
>
> I'm using Protel 99SE, which has a schematic entry package that I much
> prefer to the GHASTLY xst. There are some differences in the way
> they like to see schematics, though. Protel insists on ipads and opads,
> while ise insists on just having ports on the top level sheet.
>
> There are some other problems, like Protel puts a '&' before every symbol
> and pin name. Well, I just strip them in the editor. Oddly, Protel
> makes the
> ibuf and obuf parts disappear, so I'm converting the unwanted ipad and

opads

to ibuf and obuf. It is close, but not quite there, yet.
>
> Does anyone know of a freeware solution, have written a converter or
> have a procedure of what to do to make the conversion?
>
> Or, as another possibility, does anyone have a complete EDIF file that
> is completely acceptable to ise? (There is exactly one EDIF file in the
> entire examples dir, and it is a very complicated design, and not very
> good to use as a reference on how to construct a valid edif.
>
> Thanks much for any help you can offer!
>
> Jon
>

My problem is more with Protel than Xilinx ISE. Protel's pld software is so broken that I don't even know where to start. For instance, I put in a 16-bit shift register, and all that comes out in the EDIF file are the Q outputs of the FFs. No clock, data in or anything else show up. Fortunately, their basic schematic code works better, and the right stuff comes out, but there's extra junk, and some really inconsistent stuff.

Yes, but the net names and such pretty quickly bring you to the trouble spot.

I had planned on checking this as a base when I got to the point of making a converter program, but didn't think of using it as is to clean up the EDIF. Thanks!

Thanks for the example! I think I have the EDIF format that Xilinx needs pretty well figured out, now.

Jon

Re: EDIF input to Xilinx ISE

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