Re: quetions about configure altera fpga(apex20k) using ppa scheme

Hello, When using passive parallel asynchronous (PPA) mode, the APEX device has a built-in oscillator that controls its response to the nWS and other signals. There is some variation of this oscillator's speed depending on temperature, voltage, and process.

When you drive nWS low then high, the device captures the byte of data on the DATA[7..0] bus and then starts to process it, clocked by the internal oscillator. During this time it will drive the RDYnBSY line low. When it drives the RDYnBSY line high, it has completed.

When you drive in the final byte of data, the device will drive RDYnBSY low then high. CONF_DONE will not be released until after it has driven RDYnBSY high again. On an APEX 20KE device, tBUSY (the time during which RDYnBSY is low) ranges from 0.4 to 1.6 microseconds.

Note that the configuration files that Quartus II software generates include some number of 1s at the end of the file. The reason for doing so is that with other configuration modes (such as passive serial), the system must clock the device after CONF_DONE goes high to get it into user mode. Quartus II adds the extra bits so that a user can just drive in the whole file and by doing so clock the device enough times to initialize it - the user does not have to drive in the data and then separately clock it. A small thing but it makes it easier to use. When using PPA, this means that CONF_DONE will go high before you have sent in the entire file. If you have chosen the internal oscillator as the clock source for initializing the device, the device may even enter user mode before you have sent in the entire file. (This choice is one of the device options, chosen when you select the configuration mode).

Finally, note that depending on your use of the dual-purpose pins, there may be no harm in sending in the entire configuration file, and doing so can make the system design a little easier. For example, the data bus pins DATA[7..1] are used for configuration in PPA mode, but may take on a different functionality in user mode. If those pins are programmed to be inputs in user mode, then continuing to drive in the extra 1s at the end of the configuration file will be ok. But if they are programmed to be outputs, then you could have contention.

So the short answer to your question is that CONF_DONE will go high after RDYnBSY goes low then high again. The long answer is that depending on the overall setup, sending the extra bytes may not matter.

Sincerely, Greg Steinke snipped-for-privacy@altera.com Altera Corporation

hello,everyone,i am trying to configure apex20k200e-1x using ppa > scheme.i have read the altera databook an116.in figure 24 of page 42,i > learned that after sending the last byte ,the signal "conf_done" go > high. i want to know how much time after the nws go high,conf_done can > go high. it will result in some extra bytes being sent to apex20k if > the delay time is too long, because i check the signal conf_done to > judge whether the confige is complete.
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