Configuration Altera Decives using EPC16 in PPS mode

Hi Tal, The EPC16 should be driving out the DCLK signal, so figuring out why this does not happen is key. However it's hard to say exactly what is the problem based on this description. Here's a few things to try:

1. Make sure that the MSEL pins are set correctly on the FPGAs. PPS is the acronym for Passive Parallel Synchronous - but the setup where one EPC16 drives multiple FPGAs in parallel like this is called Concurrent Configuration, and each FPGA should be set to Passive Serial as each is receiving a serial stream.
2. Make sure the PGM pins are set correctly on the EPC16 to show which page of data you want to access. If you are not doing anything special like storing multiple configurations, they should be set to 0.
3. There are some external connections that must be made on the EPC16. The F-RP# pin must be connected to the C-RP# pin. And the F-WE# pin must be connected to the C-WE# pin. This connection is because the EPC16 actually has two dice in it - a Flash and a controller. During the production test, the Flash pins are driven to 12 V, but the controller cannot handle this, therefore the connection cannot be made in the package.
4. The FPGA VCCINT must be powered before the POR on the EPC16 expires. The POR can be set to 2 ms or 100 ms by using the PORSEL pin

- if you drive PORSEL low, then the POR is 100 ms. If this is not done, then the EPC16 will never start configuration and you will not see DCLK toggle.

Hopefully one of these solves the problem. If not, please check out the FPGA Configuration Troubleshooter found on this web site:

And if that doesn't work, then you may need to call the distributor, FAE, or AE for some more assistance as the problem debug starts to get very specific.

Sincerely, Greg Steinke Altera Corporation snipped-for-privacy@altera.com

Hi Greg,

Thank you for your reply.

Here are some more facts regarding to my board:

1. the VCCINT is stablized in about ~1mSec after power-up. the POR is configured to 100mSec.

1. all of the MSEL & PGM pins are configured correctly.

2. the EPC16 Flash interface pins (address. data etca) are connected to a HOST. first, I had problems in programing the EPC16 through ByteBlaster, So I've disbled the HOST permentlay (all of its pins are HIGH-Z always) & the programing worked!

1. I forgot to connect the nIO_PULL pin of the EP1S20 device to GND / VCC, I can't connect it because it hasn't got a VIA on the PCB, So it left un-connected.

2. I've tried power-sequencing: a. I've powered the EPC16 VCC before the FPGA's VCCINT & VCCIO & the configuration worked! b. I've tried also the opposite sequence. first, I've powered the FPGA's VCCINT & VCCIO and then I've powered the EPC16 VCC and the configuration ALSO WORKED!!!! c. when I don't have power-sequnce the configuration isn't working!!!!!!

I've talked with my distributer & he hasn't got a clue....

please advice next...

Thanks,

Tal

I have communicated with Tal about this off-line. For those of you who may see something similar - The problem was that the EPC16 address and data lines were also connected to a microprocessor. This microprocessor was supposed to tristate the lines when a certain signal was active. Once the connection between the EPC16 and the microprocessor was physically cut, then the configuration worked. So something funny is going on with the microprocessor. The reason this is a problem is that the EPC16 has the flash die and the controller die in one package. During configuration, the controller is exercising the flash. This activity is on the flash address and data pins, which are connected to external pins. So if an external device is doing something to those pins then configuration can fail. To help future customers we will add this scenario to our Configuration Troubleshooter tool on the Altera web site.

Regards, Greg Steinke snipped-for-privacy@altera.com Altera Corporation